From 6e8d0122ebac6d641304c522c5f467723a1e2468 Mon Sep 17 00:00:00 2001 From: Anand Vaikar Date: Mon, 17 Jun 2024 10:46:17 +0530 Subject: soc/amd/cezanne: Add AMD Renoir SOC support Add AMD SOC Family 17h Renoir CPUIDs per PPR doc #55922 Renoir is similar to Cezanne with only differences in CCX count. Cezanne has one Zen3 CCX with 8 cores per CCX compared to the two Zen2 CCX with 4 cores per CCX. Hence, coreboot side Cezanne SOC code should be mostly compatible with Renoir and can be leveraged. Change-Id: I6b43eb782527351c79b835d094a5b61103cd6642 Signed-off-by: Anand Vaikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/83099 Reviewed-by: Felix Held Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/cpu.c | 1 + src/soc/amd/cezanne/include/soc/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 2c3100fc81..4f39aefc75 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -24,6 +24,7 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, CEZANNE_A0_CPUID, CPUID_ALL_STEPPINGS_MASK }, + { X86_VENDOR_AMD, RENOIR_A1_CPUID, CPUID_ALL_STEPPINGS_MASK}, CPU_TABLE_END }; diff --git a/src/soc/amd/cezanne/include/soc/cpu.h b/src/soc/amd/cezanne/include/soc/cpu.h index 0239e19fe9..1506420ad4 100644 --- a/src/soc/amd/cezanne/include/soc/cpu.h +++ b/src/soc/amd/cezanne/include/soc/cpu.h @@ -4,6 +4,7 @@ #define AMD_CEZANNE_CPU_H #define CEZANNE_A0_CPUID CPUID_FROM_FMS(0x19, 0x50, 0) +#define RENOIR_A1_CPUID CPUID_FROM_FMS(0X17, 0X60, 1) #define CEZANNE_VBIOS_VID_DID 0x10021638 #define BARCELO_VBIOS_VID_DID 0x100215e7 -- cgit v1.2.3