From 6cdc838b0d39398ff7662e425ed330fdc1e3333c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Wed, 27 Oct 2021 23:04:07 +0530
Subject: soc/intel/common: Add DDR5 and LPDDR5 into the SMBIOS table

Add DDR5 and LPDDR5 memory technology into the SMBIOS Memory Type
table.

Change-Id: I1ec442cf0bd830db99e3636445724b6be01c5564
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/include/smbios.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/include/smbios.h b/src/include/smbios.h
index 2fb6297ea3..c11fc6c658 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -192,6 +192,8 @@ typedef enum {
 	MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f,
 	MEMORY_TYPE_HBM = 0x20,
 	MEMORY_TYPE_HBM2 = 0x21,
+	MEMORY_TYPE_DDR5 = 0x22,
+	MEMORY_TYPE_LPDDR5 = 0x23,
 } smbios_memory_type;
 
 typedef enum {
-- 
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