From 6ae4d2e0a6a3cb8a1420cade9367393d121f0008 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 12 Oct 2022 17:48:47 +0000 Subject: Revert "soc/qualcomm: Update the wait time for checking PCIe link up" This reverts commit 4b5ba9436373d1addab13cd38ee6899e49ea029f. Reason for revert: This optimization is causing the non-serial enabled tot BIOS to not boot. To get tot back into good shape, will revert for now and reevalute this fix and resubmit at a later time. BUG=b:218406702 BRANCH=None TEST=reboot from AP console (on herobrine) after flashing image-herobrine.bin. prior to fix the device would never boot to login prompt. after rever the device would boot to login prompt again. Change-Id: Iaac5f2fb2120f6aa41a0ce9a763d50fd7b9a3ec7 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/68339 Tested-by: build bot (Jenkins) Reviewed-by: Douglas Anderson --- src/soc/qualcomm/common/include/soc/pcie.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/qualcomm/common/include/soc/pcie.h b/src/soc/qualcomm/common/include/soc/pcie.h index 5aa315cca5..09ea6712dc 100644 --- a/src/soc/qualcomm/common/include/soc/pcie.h +++ b/src/soc/qualcomm/common/include/soc/pcie.h @@ -48,8 +48,8 @@ #define LINK_SPEED_GEN_1 0x1 #define LINK_SPEED_GEN_2 0x2 #define LINK_SPEED_GEN_3 0x3 -#define PCIE_LINK_UP_MS 10 -#define LINK_WAIT_MAX_RETRIES 100 +#define PCIE_LINK_UP_MS 100 +#define LINK_WAIT_MAX_RETRIES 10 #define COMMAND_MASK 0xffff -- cgit v1.2.3