From 69c2811acc685f1d46aff081583af039388f7aab Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@google.com>
Date: Tue, 28 Apr 2020 18:57:52 -0700
Subject: soc/amd/picasso: Allow mainboard to configure SPI settings

This change adds options to allow mainboard to configure SPI speed for
different modes as well as the SPI read mode.

BUG=b:153675510,b:147758054
BRANCH=trembyle-bringup
TEST=Verified that SPI settings are configured correctly for trembyle.

Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/picasso/chip.h        | 16 ++++++++++++++++
 src/soc/amd/picasso/southbridge.c |  8 ++++++--
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 4cc10ef945..edb1b69bb0 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -10,6 +10,7 @@
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <soc/i2c.h>
 #include <soc/iomap.h>
+#include <soc/southbridge.h>
 #include <arch/acpi_device.h>
 
 struct soc_amd_picasso_config {
@@ -70,6 +71,21 @@ struct soc_amd_picasso_config {
 	uint8_t core_dldo_bypass;
 	uint8_t min_soc_vid_offset;
 	uint8_t aclk_dpm0_freq_400MHz;
+
+	/*
+	 * SPI config
+	 * Default values if not overridden by mainboard:
+	 * Read mode - Normal 33MHz
+	 * Normal speed - 66MHz
+	 * Fast speed - 66MHz
+	 * Alt speed - 66MHz
+	 * TPM speed - 66MHz
+	 */
+	enum spi_read_mode spi_read_mode;
+	enum spi100_speed spi_normal_speed;
+	enum spi100_speed spi_fast_speed;
+	enum spi100_speed spi_altio_speed;
+	enum spi100_speed spi_tpm_speed;
 };
 
 typedef struct soc_amd_picasso_config config_t;
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index c38f373a36..4f25802141 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -23,6 +23,7 @@
 #include <soc/pci_devs.h>
 #include <soc/nvs.h>
 #include <types.h>
+#include "chip.h"
 
 #define FCH_AOAC_UART_FOR_CONSOLE \
 		(CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \
@@ -237,8 +238,11 @@ void sb_read_mode(u32 mode)
 
 static void sb_spi_config_modes(void)
 {
-	sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M,
-		      SPI_SPEED_16M, SPI_SPEED_16M);
+	const struct soc_amd_picasso_config *cfg = config_of_soc();
+
+	sb_read_mode(cfg->spi_read_mode);
+	sb_set_spi100(cfg->spi_normal_speed, cfg->spi_fast_speed, cfg->spi_altio_speed,
+		      cfg->spi_tpm_speed);
 }
 
 static void sb_spi_init(void)
-- 
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