From 66d5b924405010b48121dba54b781886546538d7 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 13 Apr 2017 17:02:58 -0500 Subject: sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used Do not map LPC ROM into the system memory space when SPI Flash is configured instead of an LPC ROM. This resolves a long-standing hard boot hang issue on the ASUS KGPE-D16 and related systems; in a nutshell, the incorrectly mapped LPC ROM overrode low memory required by ramstage, causing decompressed ramstage layout-dependent vectoring to romstage code and subsequent execution of random sections of romstage. Sometimes these random sections of romstage reconfigured the hardware in such a way that it could not access SPI Flash on the next boot attempt. Change-Id: I115e5d834f0ca99c2d9dbb5b9b5badbea1d98574 Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/19280 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Paul Menzel Reviewed-by: Daniel Kulesz --- src/southbridge/amd/sb700/bootblock.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index dfa4102953..e77db5ced9 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -44,15 +44,13 @@ static void sb700_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); - /* The LPC settings below work for SPI flash as well; - * the hardware does not distinguish between LPC and SPI flash ROM - * aside from offering additional side-channel access to SPI flash - * via a separate register-based interface. - */ - - /* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5); - reg8 |= (1 << 3) | (1 << 4); + if (IS_ENABLED(CONFIG_SPI_FLASH)) + /* Disable decode of variable LPC ROM address ranges 1 and 2. */ + reg8 &= ~((1 << 3) | (1 << 4)); + else + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 |= (1 << 3) | (1 << 4); pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8); /* LPC ROM address range 1: */ -- cgit v1.2.3