From 6527b1acc7a020e1f0594a7ea30daed0978dd5fd Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 29 Jan 2019 11:04:25 +0530 Subject: soc/intel/cannonlake: Add Whiskeylake SoC kconfig This patch performs below tasks 1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig. 2. Allow required SoC to select this kconfig to extend CANNONLAKE SoC support and add incremental changes. 3. Select correct SoC support for hatch, sarien, cflrvps and whlrvp. * Hatch is WHL SoC based board * Sarien is WHL SoC based board * CFLRVP U/8/11 are CFL SoC based board * WHLRVP is based on WHL SoC 4. Add correct FSP blobs path for WHL SoC based designs. Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/31133 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: Furquan Shaikh --- src/drivers/intel/fsp2_0/Kconfig | 2 +- src/mainboard/google/hatch/Kconfig | 2 +- src/mainboard/google/sarien/Kconfig | 2 +- src/mainboard/intel/coffeelake_rvp/Kconfig | 1 - src/mainboard/intel/coffeelake_rvp/Kconfig.name | 4 ++++ src/soc/intel/cannonlake/Kconfig | 28 +++++++++++++++++++++---- src/soc/intel/cannonlake/chip.h | 4 +--- src/soc/intel/cannonlake/romstage/fsp_params.c | 2 +- 8 files changed, 33 insertions(+), 12 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d187dc..60fed37eb1 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,7 @@ config FSP_USE_REPO bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COMMON_CANNONLAKE_BASE help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 01f8e09361..65a3562a2f 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -14,7 +14,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_COFFEELAKE + select SOC_INTEL_WHISKEYLAKE select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 1216f2da60..dc8f486104 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -16,7 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK - select SOC_INTEL_COFFEELAKE + select SOC_INTEL_WHISKEYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS select SPD_READ_BY_WORD diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index fbfcc0fc1f..d2d4b81013 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS select GENERIC_SPD_BIN select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC - select SOC_INTEL_COFFEELAKE select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_WHISKEYLAKE_RVP select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 773c83acc0..70652eff66 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -2,9 +2,13 @@ comment "Coffeelake RVP" config BOARD_INTEL_COFFEELAKE_RVPU bool "-> Coffeelake U SO-DIMM DDR4 RVP" + select SOC_INTEL_COFFEELAKE config BOARD_INTEL_COFFEELAKE_RVP11 bool "-> Coffeelake H SO-DIMM DDR4 RVP11" + select SOC_INTEL_COFFEELAKE config BOARD_INTEL_WHISKEYLAKE_RVP bool "-> Whiskeylake U DDR4 RVP" + select SOC_INTEL_WHISKEYLAKE config BOARD_INTEL_COFFEELAKE_RVP8 bool "-> Coffeelake S U-DIMM DDR4 RVP8" + select SOC_INTEL_COFFEELAKE diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 0a1cff0938..cd8819d2cc 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -3,13 +3,33 @@ config SOC_INTEL_CANNONLAKE help Intel Cannonlake support -config SOC_INTEL_COFFEELAKE +config SOC_INTEL_COMMON_CANNONLAKE_BASE bool default n select SOC_INTEL_CANNONLAKE + help + Single Kconfig option to select common base Cannonlake support. + This Kconfig will help to select majority of CNL SoC features. + Major difference that exist today between + SOC_INTEL_COMMON_CANNONLAKE_BASE and SOC_INTEL_CANNONLAKE Kconfig + are in FSP Header Files. Hence this Kconfig might help to select + required SoC support FSP headers. Any future Intel SoC would + like to make use of CNL support might just select this Kconfig. + +config SOC_INTEL_COFFEELAKE + bool + default n + select SOC_INTEL_COMMON_CANNONLAKE_BASE help Intel Coffeelake support +config SOC_INTEL_WHISKEYLAKE + bool + default n + select SOC_INTEL_COMMON_CANNONLAKE_BASE + help + Intel Whiskeylake support + config SOC_INTEL_CANNONLAKE_PCH_H bool default n @@ -244,12 +264,12 @@ endchoice config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if !SOC_INTEL_COFFEELAKE - default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE + default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE + default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE endif diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f312c6f2ea..cb9ad3827f 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -36,8 +36,6 @@ #include #endif - - struct soc_intel_cannonlake_config { /* Common struct containing soc config data required by common code */ @@ -109,7 +107,7 @@ struct soc_intel_cannonlake_config { enum { SaGv_Disabled, SaGv_FixedLow, -#if !IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) +#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) SaGv_FixedMid, #endif SaGv_FixedHigh, diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index bdaa4afaf1..b8b2c1798c 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -53,7 +53,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->VmxEnable = 0; else m_cfg->VmxEnable = config->VmxEnable; -#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif -- cgit v1.2.3