From 62347c4669937ea47200fd677ad0368f6e289495 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 9 Jul 2024 23:15:39 +0530 Subject: soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-M This patch updates FSP-M UPDs conditionally to ensure CSE firmware updates and VGA initialization control only when `SOC_INTEL_CSE_LITE_SKU` config is enabled. This ensures eSOL rendering is tied to CSE sync performed in coreboot, preventing unnecessary setup when sync is deferred to the payload. Deferring CSE sync to the payload results in the depthcharge screen. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/soc/intel/meteorlake/romstage/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index ec0bb8dae6..ec783833ba 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -454,7 +454,7 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, sol_type = ELOG_FW_EARLY_SOL_MRC; } - if (is_cse_fw_update_required()) { + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) { vga_init_control = VGA_INIT_CONTROL_ENABLE; sol_type = ELOG_FW_EARLY_SOL_CSE_SYNC; } -- cgit v1.2.3