From 612a8676779f873f2f7a3c8011ad0eac61ca38f9 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 19 Feb 2019 19:11:29 +0100 Subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers Instead of adding more versions of the `*pch.asl`, unify the existing ones and allow to override the register locations via Kconfig. The current defaults should work for Skylake and some newer platforms. TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/31503 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Wim Vervoorn Reviewed-by: Benjamin Doron --- src/drivers/intel/gma/Kconfig | 16 ++++++++++++ src/drivers/intel/gma/acpi/gma.asl | 30 ++++++++++++++++++++++ src/drivers/intel/gma/acpi/non-pch.asl | 29 --------------------- src/drivers/intel/gma/acpi/pch.asl | 30 ---------------------- src/northbridge/intel/gm45/Kconfig | 6 +++++ src/northbridge/intel/gm45/acpi/gm45.asl | 2 +- src/northbridge/intel/haswell/Kconfig | 3 +++ src/northbridge/intel/haswell/acpi/haswell.asl | 2 +- src/northbridge/intel/ironlake/Kconfig | 3 +++ src/northbridge/intel/ironlake/acpi/ironlake.asl | 2 +- src/northbridge/intel/sandybridge/Kconfig | 3 +++ .../intel/sandybridge/acpi/sandybridge.asl | 2 +- src/northbridge/intel/x4x/acpi/x4x.asl | 2 +- 13 files changed, 66 insertions(+), 64 deletions(-) create mode 100644 src/drivers/intel/gma/acpi/gma.asl delete mode 100644 src/drivers/intel/gma/acpi/non-pch.asl delete mode 100644 src/drivers/intel/gma/acpi/pch.asl diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 68d4edce03..acc25fea29 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -29,6 +29,22 @@ config INTEL_GMA_ACPI bool default n +config INTEL_GMA_BCLV_OFFSET + hex + default 0xc8254 + +config INTEL_GMA_BCLV_WIDTH + int + default 16 + +config INTEL_GMA_BCLM_OFFSET + hex + default 0xc8256 + +config INTEL_GMA_BCLM_WIDTH + int + default 16 + config INTEL_GMA_SSC_ALTERNATE_REF bool default n diff --git a/src/drivers/intel/gma/acpi/gma.asl b/src/drivers/intel/gma/acpi/gma.asl new file mode 100644 index 0000000000..57563933ce --- /dev/null +++ b/src/drivers/intel/gma/acpi/gma.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64, + Offset (0xe4), + ASLE, 32, + Offset (0xfc), + ASLS, 32, + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (CONFIG_INTEL_GMA_BCLV_OFFSET), + BCLV, CONFIG_INTEL_GMA_BCLV_WIDTH, + Offset (CONFIG_INTEL_GMA_BCLM_OFFSET), + BCLM, CONFIG_INTEL_GMA_BCLM_WIDTH + } + +#include "configure_brightness_levels.asl" +#include "common.asl" +} diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl deleted file mode 100644 index b656d484c9..0000000000 --- a/src/drivers/intel/gma/acpi/non-pch.asl +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -Device (GFX0) -{ - Name (_ADR, 0x00020000) - - OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) - Field (GFXC, DWordAcc, NoLock, Preserve) - { - Offset (0x10), - BAR0, 64, - Offset (0xe4), - ASLE, 32, - Offset (0xfc), - ASLS, 32, - } - - OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) - Field (GFRG, DWordAcc, NoLock, Preserve) - { - Offset (0x61254), - BCLV, 16, - BCLM, 16, - } - -#include "configure_brightness_levels.asl" -#include "common.asl" -} diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl deleted file mode 100644 index 942ccf433c..0000000000 --- a/src/drivers/intel/gma/acpi/pch.asl +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -Device (GFX0) -{ - Name (_ADR, 0x00020000) - - OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) - Field (GFXC, DWordAcc, NoLock, Preserve) - { - Offset (0x10), - BAR0, 64, - Offset (0xe4), - ASLE, 32, - Offset (0xfc), - ASLS, 32, - } - - OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) - Field (GFRG, DWordAcc, NoLock, Preserve) - { - Offset (0x48254), - BCLV, 16, - Offset (0xc8256), - BCLM, 16 - } - -#include "configure_brightness_levels.asl" -#include "common.asl" -} diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 752af43ba1..8857bd4f9b 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -46,4 +46,10 @@ config SMM_RESERVED_SIZE hex default 0x100000 +config INTEL_GMA_BCLV_OFFSET + default 0x61254 + +config INTEL_GMA_BCLM_OFFSET + default 0x61256 + endif diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 3a7e46487d..8a30212d1d 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -75,4 +75,4 @@ Device (PDRC) #include "peg.asl" // Integrated graphics 0:2.0 -#include +#include diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 5e631cf025..06ce371946 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -107,4 +107,7 @@ config RO_REGION_ONLY depends on VBOOT default "mrc.bin" +config INTEL_GMA_BCLV_OFFSET + default 0x48254 + endif diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index c0de8532fd..900c6c3396 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -48,4 +48,4 @@ Device (PDRC) } // Integrated graphics 0:2.0 -#include +#include diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index 638f295dc0..9d937965dd 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -61,4 +61,7 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000 +config INTEL_GMA_BCLV_OFFSET + default 0x48254 + endif diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 52fec1e731..2997dea951 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -51,4 +51,4 @@ Device (PDRC) } // Integrated graphics 0:2.0 -#include +#include diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index a9bbf58ef8..29a6db7fb3 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -121,4 +121,7 @@ config MRC_FILE endif # !USE_NATIVE_RAMINIT +config INTEL_GMA_BCLV_OFFSET + default 0x48254 + endif diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 555058cbe6..202671a3e5 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -55,4 +55,4 @@ Device (PDRC) } // Integrated graphics 0:2.0 -#include +#include diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 5f93b3eee3..09849e3b17 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -45,4 +45,4 @@ Device (PDRC) #include "peg.asl" // Integrated graphics 0:2.0 -#include +#include -- cgit v1.2.3