From 61234909f8ac02f3a0a5af2826a9b5b702a2bb9e Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 31 Jul 2015 17:27:23 +0200 Subject: imgtech/pistacho: Add vboot2 memory region Change-Id: I375397d4a1db6fef6b40421590f315c0f7eb0948 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/11100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index b36d47e9b6..366b20ac91 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -18,6 +18,7 @@ */ #include +#include #include @@ -39,7 +40,8 @@ SECTIONS */ SRAM_START(0x1a000000) ROMSTAGE(0x1a005000, 40K) - PRERAM_CBFS_CACHE(0x1a00f000, 68K) + VBOOT2_WORK(0x1a00f000, 12K) + PRERAM_CBFS_CACHE(0x1a012000, 56K) SRAM_END(0x1a020000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. -- cgit v1.2.3