From 6085d39bdb2c23f91fdda752d96e37a57fef8f82 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 9 Jan 2019 16:42:07 +0100 Subject: util/superiotool: Add ITE8528 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ITE8528 which can be found on the wedge100s. Most registers are dumped from hardware. No datasheet is publicy available. Change-Id: I24b12c0032157a4959336f8b51dadbe7b2e09d66 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/30801 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Felix Held Reviewed-by: Angel Pons --- util/superiotool/ite.c | 56 ++++++++++++++++++++++++++++++++++++++++++ util/superiotool/superiotool.h | 2 +- 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index d24a2bfa27..06efc5787d 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -273,6 +273,62 @@ static const struct superio_registers reg_table[] = { {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}}, {EOT}}}, + {0x8528, "IT8528", { + {NOLDN, NULL, + {0x24,0x25,0x26,0x27,0x28,0x29, + 0x2A,0x2B,0x2C,0x2D,0x2E,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,EOT}}, + {NOLDN, "Chip ID", + {0x20,0x21, EOT}, + {0x85,0x28, EOT}}, + {NOLDN, "Chip Version", + {0x22,EOT}, + {0x0a,EOT}}, + {NOLDN, "Super I/O Control Register (SIOCTRL)", + {0x23,EOT}, + {0x01,EOT}}, + {0x01, "UART1", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x03,0xf8,0x00,0x00,0x04,0x02,EOT}}, + {0x02, "UART2", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x02,0xf8,0x00,0x00,0x03,0x02,EOT}}, + {0x04, "System Wake-Up (SWUC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x01,EOT}}, + {0x05, "Mouse", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x0C,0x01,EOT}}, + {0x06, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}}, + {0x0f, "Shared Memory/Flash Interface (SMFI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71, + 0xf4,0xf5,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00, + NANA,NANA,EOT}}, + {0x10, "BRAM / Real Time Clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71, + 0xf1,0xf2,0xf3,0xf4,0xf5,EOT}, + {0x00,0x00,0x70,0x00,0x72,0x08,0x01, + NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x11, "Power Channel 1", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x12, "Power Channel 2", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x01,0x01,EOT}}, + {0x17, "Power Channel 3", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}}, + {0x18, "Power Channel 4", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x74,0x00,0x78,0x01,0x01,EOT}}, + {0x19, "Power Channel 5", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x7a,0x00,0x7c,0x01,0x01,EOT}}, + {EOT}}}, {0x8623, "IT8623E", { /* Defaults are not specified as no datasheet available */ {NOLDN, NULL, diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index ed7beae6b8..1a10fb63ab 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -241,7 +241,7 @@ static const struct { {probe_idregs_fintek, {0x2e, 0x4e, EOT}}, {probe_idregs_fintek_alternative, {0x2e, 0x4e, EOT}}, /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */ - {probe_idregs_ite, {0x20e, 0x25e, 0x2e, 0x4e, 0x370, EOT}}, + {probe_idregs_ite, {0x20e, 0x25e, 0x2e, 0x4e, 0x370, 0x6e, EOT}}, {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, 0x164e, EOT}}, /* I/O pairs on Nuvoton EC chips can be configured by firmware in * addition to the following hardware strapping options. */ -- cgit v1.2.3