From 5f46af6325b5facb9a608b0f86595b92b98ed718 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 24 Jun 2017 13:24:26 -0600 Subject: cpu/amd: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I9f4155285529ec28e826637a61436478f648704c Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20335 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/amd/agesa/amd_late_init.c | 4 +-- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/cpu/amd/dualcore/dualcore.c | 4 +-- src/cpu/amd/family_10h-family_15h/fidvid.c | 17 ++++++----- src/cpu/amd/family_10h-family_15h/init_cpus.c | 28 +++++++++--------- .../amd/family_10h-family_15h/model_10xxx_init.c | 4 +-- src/cpu/amd/geode_gx2/syspreinit.c | 2 +- src/cpu/amd/geode_lx/syspreinit.c | 2 +- src/cpu/amd/model_fxx/fidvid.c | 34 +++++++++++----------- src/cpu/amd/model_fxx/init_cpus.c | 24 +++++++-------- src/cpu/amd/model_fxx/microcode_blob.c | 2 +- src/cpu/amd/model_fxx/model_fxx_init.c | 10 +++---- src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 4 +-- src/cpu/amd/model_fxx/powernow_acpi.c | 2 +- src/cpu/amd/model_fxx/processor_name.c | 12 ++++---- src/cpu/amd/pi/00630F01/model_15_init.c | 4 +-- src/cpu/amd/pi/00660F01/model_15_init.c | 4 +-- src/cpu/amd/pi/00670F00/model_15_init.c | 4 +-- src/cpu/amd/pi/00730F01/model_16_init.c | 4 +-- src/cpu/amd/quadcore/quadcore.c | 2 +- 20 files changed, 85 insertions(+), 84 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index a55ebd896f..9bb6b2784e 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -18,7 +18,7 @@ #include -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) #include #endif @@ -29,7 +29,7 @@ static void agesawrapper_post_device(void *unused) agesawrapper_amdinitlate(); -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) sb_Late_Post(); #endif if (!acpi_s3_resume_allowed()) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 156333f12c..e48d25c0a0 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -143,7 +143,7 @@ CAR_FAM10_out: CAR_FAM10_errata_applied: -#if CONFIG_MMCONF_SUPPORT +#if IS_ENABLED(CONFIG_MMCONF_SUPPORT) #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF) #error "MMCONF_BASE_ADDRESS too big" #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF) diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 1f25668c54..a388354e9e 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -15,7 +15,7 @@ #include "cpu/amd/dualcore/dualcore_id.c" #include -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -30,7 +30,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid) static inline uint8_t set_apicid_cpuid_lo(void) { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) if (is_cpu_pre_e0()) return 0; // pre_e0 can not be set #endif diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 126271875b..12fc2c7f21 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -94,21 +94,21 @@ b.- prep_fid_change(...) static inline void print_debug_fv(const char *str, u32 val) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -503,7 +503,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, } /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ - #if CONFIG_SVI_HIGH_FREQ + #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ) if (cpuRev & AMD_FAM10_C3) { dword |= SVI_HIGH_FREQ_ON; } @@ -583,7 +583,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, if (cpuRev & AMD_DR_Bx ) { smaf001 = 0xA6; } else { - #if CONFIG_SVI_HIGH_FREQ + #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ) if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { smaf001 = 0xF6; } @@ -1034,7 +1034,7 @@ void init_fidvid_stage2(u32 apicid, u32 nodeid) } -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st { u32 num; // it could use 256 bytes for 64 node quad core system @@ -1053,7 +1053,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp) int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st ap_apicidx; u32 i; #endif @@ -1068,7 +1068,8 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) print_debug_fv("BSP fid = ", fv.common_fid); -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \ + !IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) /* For all APs (We know the APIC ID of all APs even when the APIC ID is lifted) remote read from AP LAPIC_MSG_REG about max fid. Then calculate the common max fid that can be used for all diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 2f90f430f2..c151aac5d1 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -16,7 +16,7 @@ #include "init_cpus.h" -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif #include @@ -36,7 +36,7 @@ #include "cpu/amd/car/post_cache_as_ram.c" -#if CONFIG_PCI_IO_CFG_EXT +#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) static void set_EnableCf8ExtCfg(void) { // set the NB_CFG[46]=1; @@ -152,7 +152,7 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, /* get_nodes define in ht_wrapper.c */ nodes = get_nodes(); - if (!CONFIG_LOGICAL_CPUS || + if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) || read_option(multi_core, 0) != 0) { // 0 means multi core disable_siblings = 1; } else { @@ -182,8 +182,8 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, for (j = jstart; j <= jend; j++) { ap_apicid = get_boot_apic_id(i, j); -#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0) -#if !CONFIG_LIFT_BSP_APIC_ID +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) +#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -227,7 +227,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) return result; } -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); #endif @@ -398,17 +398,17 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) if (!is_fam15h()) set_apicid_cpuid_lo(); set_EnableCf8ExtCfg(); -#if CONFIG_ENABLE_APIC_EXT_ID +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) enable_apic_ext_id(id.nodeid); #endif } enable_lapic(); -#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0) +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); -#if !CONFIG_LIFT_BSP_APIC_ID +#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) if (initial_apicid != 0) // other than bsp #endif { @@ -420,7 +420,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) lapic_write(LAPIC_ID, dword); } -#if CONFIG_LIFT_BSP_APIC_ID +#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif @@ -473,8 +473,8 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) } } -#if CONFIG_SET_FIDVID -#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY +#if IS_ENABLED(CONFIG_SET_FIDVID) +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) // Run on all AP for proper FID/VID setup. if (id.coreid == 0) // only need set fid for core0 #endif @@ -574,7 +574,7 @@ static void start_node(u8 node) /* Enable routing table */ printk(BIOS_DEBUG, "Start node %02x", node); -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) /* For FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); @@ -1865,7 +1865,7 @@ void finalize_node_setup(struct sys_info *sysinfo) cpuSetAMDPCI(i); } -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) // Prep each node for FID/VID setup. prep_fid_change(); #endif diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index b002b62548..361a866638 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -64,7 +64,7 @@ static void model_10xxx_init(device_t dev) u8 i; msr_t msr; struct node_core_id id; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif uint8_t delay_start; @@ -124,7 +124,7 @@ static void model_10xxx_init(device_t dev) /* Set the processor name string */ init_processor_name(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/geode_gx2/syspreinit.c b/src/cpu/amd/geode_gx2/syspreinit.c index 350e6df513..aa1a39d477 100644 --- a/src/cpu/amd/geode_gx2/syspreinit.c +++ b/src/cpu/amd/geode_gx2/syspreinit.c @@ -26,7 +26,7 @@ static void StartTimer1(void) void SystemPreInit(void) { /* they want a jump ... */ -#if !CONFIG_CACHE_AS_RAM +#if !IS_ENABLED(CONFIG_CACHE_AS_RAM) __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); diff --git a/src/cpu/amd/geode_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c index 4a59d02c66..de6e141a94 100644 --- a/src/cpu/amd/geode_lx/syspreinit.c +++ b/src/cpu/amd/geode_lx/syspreinit.c @@ -32,7 +32,7 @@ static void StartTimer1(void) void SystemPreInit(void) { /* they want a jump ... */ -#if !CONFIG_CACHE_AS_RAM +#if !IS_ENABLED(CONFIG_CACHE_AS_RAM) __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 20d090623d..371d4b933d 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) #ifndef SB_VFSMAF #define SB_VFSMAF 1 @@ -21,21 +21,21 @@ static inline void print_debug_fv(const char *str, u32 val) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -59,7 +59,7 @@ static void enable_fid_change(void) /* disable the DRAM interface at first, it will be enabled * by raminit again (see also erratum #181) */ -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94); dword |= (1 << 14); pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword); @@ -76,7 +76,7 @@ static void enable_fid_change(void) // dword = 0x00070000; /* enable FID/VID change */ pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x80, dword); -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) dword = 0x21132113; #else dword = 0x00132113; @@ -86,7 +86,7 @@ static void enable_fid_change(void) } } -#if !CONFIG_SET_FIDVID_ONE_BY_ONE +#if !IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) static unsigned set_fidvid_without_init(unsigned fidvid) { msr_t msr; @@ -292,7 +292,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) ldtstop_sb(); #endif -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) if (showmessage) { print_debug_fv_8("set_fidvid APICID = ", apicid); print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo); @@ -306,7 +306,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) } fid_cur = msr.lo & 0x3f; -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) if (showmessage) { print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo); } @@ -387,7 +387,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */ send |= (apicid << 24); /* ap apicid */ -#if CONFIG_SET_FIDVID_ONE_BY_ONE +#if IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; @@ -418,7 +418,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) } if (loop > 0) { -#if CONFIG_SET_FIDVID_ONE_BY_ONE +#if IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP #else readback = set_fidvid_without_init(readback & 0xffff00); // this AP @@ -521,7 +521,7 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp) print_debug_fv("\treadback=", readback); } -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st { u32 num; unsigned apicid[16]; /* 8 way dual core need 16 */ @@ -543,7 +543,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) struct fidvid_st fv; -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st ap_apicidx; unsigned i; #endif @@ -573,7 +573,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) /* calculate the common max fid/vid that could be used for * all APs and BSP */ -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) ap_apicidx.num = 0; for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); @@ -609,7 +609,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) #endif -#if CONFIG_SET_FIDVID_ONE_BY_ONE +#if IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); @@ -623,7 +623,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) fv.common_fidvid &= 0xffff00; /* set state 2 allow is in init_fidvid_bsp_stage2 */ -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv); } @@ -631,7 +631,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); #endif -#if !CONFIG_SET_FIDVID_ONE_BY_ONE +#if !IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 035453e652..48920bba6f 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -15,7 +15,7 @@ #include #include "cpu/amd/car/post_cache_as_ram.c" -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -61,7 +61,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, 3); if (nb_cfg_54) { if (j == 0) { // if it is single core, we need to increase siblings for APIC calculation -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 @@ -93,8 +93,8 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, i * (nb_cfg_54 ? (siblings + 1) : 1) + j * (nb_cfg_54 ? 1 : 8); -#if CONFIG_ENABLE_APIC_EXT_ID -#if !CONFIG_LIFT_BSP_APIC_ID +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) +#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -140,7 +140,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) #define LAPIC_MSG_REG 0x380 -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) static void init_fidvid_ap(u32 bsp_apicid, u32 apicid); #endif @@ -223,7 +223,7 @@ static void STOP_CAR_AND_CPU(void) stop_this_cpu(); } -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) #else static u32 init_cpus(u32 cpu_init_detectedx) @@ -265,10 +265,10 @@ static u32 init_cpus(u32 cpu_init_detectedx) enable_lapic(); // init_timer(); // We need TMICT to pass msg for FID/VID change -#if CONFIG_ENABLE_APIC_EXT_ID +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) u32 initial_apicid = get_initial_apicid(); -#if !CONFIG_LIFT_BSP_APIC_ID +#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) if (initial_apicid != 0) // other than bsp #endif { @@ -280,7 +280,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) lapic_write(LAPIC_ID, dword); } -#if CONFIG_LIFT_BSP_APIC_ID +#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif @@ -315,8 +315,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) u32 timeout = 1; u32 loop = 100; -#if CONFIG_SET_FIDVID -#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY +#if IS_ENABLED(CONFIG_SET_FIDVID) +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) if (id.coreid == 0) // only need set fid for core0 #endif init_fidvid_ap(bsp_apicid, apicid); @@ -333,7 +333,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) } lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) #if CONFIG_MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, (unsigned)STOP_CAR_AND_CPU); diff --git a/src/cpu/amd/model_fxx/microcode_blob.c b/src/cpu/amd/model_fxx/microcode_blob.c index 691ae83d14..98b418b84b 100644 --- a/src/cpu/amd/model_fxx/microcode_blob.c +++ b/src/cpu/amd/model_fxx/microcode_blob.c @@ -12,7 +12,7 @@ */ unsigned char microcode[] __attribute__ ((aligned(16))) = { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) #include "../../../../3rdparty/blobs/cpu/amd/model_fxx/microcode.h" #endif }; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 8f4bae2d96..c21bce69e3 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -39,10 +39,10 @@ #include #include -#if CONFIG_WAIT_BEFORE_CPUS_INIT +#if IS_ENABLED(CONFIG_WAIT_BEFORE_CPUS_INIT) void cpus_ready_for_init(void) { -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) #if CONFIG_MEM_TRAIN_SEQ == 1 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // wait for ap memory to trained @@ -511,7 +511,7 @@ static void model_fxx_init(device_t dev) /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { @@ -559,7 +559,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */ { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */ { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */ @@ -601,7 +601,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */ #endif -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) /* * AMD F0 support. * diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 4b70e58f18..6ae055b0a8 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -26,7 +26,7 @@ struct id_mapping { static u16 get_equivalent_processor_rev_id(u32 orig_id) { static const struct id_mapping id_mapping_table[] = { - #if !CONFIG_K8_REV_F_SUPPORT + #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) { 0x0f48, 0x0048 }, { 0x0f58, 0x0048 }, @@ -49,7 +49,7 @@ static u16 get_equivalent_processor_rev_id(u32 orig_id) { { 0x20fb1, 0x0210 }, #endif - #if CONFIG_K8_REV_F_SUPPORT + #if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) /* FIXME * Microcode files for CPU revision 0xf do * not seem to be available... diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 9979055b2d..c71835157e 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -69,7 +69,7 @@ static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, acpigen_pop_len(); } -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) /* * Details about this algorithm , refer to BDKG 10.5.1 * Two parts are included, the another is the DSDT reconstruction process diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c index 60dbf6ecb1..de6a514103 100644 --- a/src/cpu/amd/model_fxx/processor_name.c +++ b/src/cpu/amd/model_fxx/processor_name.c @@ -39,7 +39,7 @@ * your mainboard will not be posted on the AMD Recommended Motherboard Website */ -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) static const char *processor_names[]={ /* 0x00 */ "AMD Engineering Sample", /* 0x01-0x03 */ NULL, NULL, NULL, @@ -99,7 +99,7 @@ static const char *processor_names[]={ int init_processor_name(void) { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) u32 EightBitBrandId; #endif u32 BrandId; @@ -113,7 +113,7 @@ int init_processor_name(void) char program_string[48]; unsigned int *program_values = (unsigned int *)program_string; -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) /* Find out which CPU brand it is */ EightBitBrandId = cpuid_ebx(0x00000001) & 0xff; BrandId = cpuid_ebx(0x80000001) & 0xffff; @@ -137,7 +137,7 @@ int init_processor_name(void) processor_name_string = "AMD Processor model unknown"; #endif -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) u32 Socket; u32 CmpCap; u32 PwrLmt; @@ -394,7 +394,7 @@ int init_processor_name(void) for (i=0; i<47; i++) { // 48 -1 if (program_string[i] == program_string[i+1]) { switch (program_string[i]) { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) case 'X': ModelNumber = 22+ NN; break; case 'Y': ModelNumber = 38 + (2*NN); break; case 'Z': @@ -403,7 +403,7 @@ int init_processor_name(void) case 'V': ModelNumber = 9 + NN; break; #endif -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) case 'R': ModelNumber = NN - 1; break; case 'P': ModelNumber = 26 + NN; break; case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break; diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index c2f2e9d39e..317aca8ea5 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -39,7 +39,7 @@ static void model_15_init(device_t dev) msr_t msr; int msrno; unsigned int cpu_idx; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -79,7 +79,7 @@ static void model_15_init(device_t dev) /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index c31dec8b03..8f739cf3b6 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -54,7 +54,7 @@ static void model_15_init(device_t dev) u8 i; msr_t msr; int msrno; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -93,7 +93,7 @@ static void model_15_init(device_t dev) /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c index 02e5b79e84..5550b9915a 100644 --- a/src/cpu/amd/pi/00670F00/model_15_init.c +++ b/src/cpu/amd/pi/00670F00/model_15_init.c @@ -54,7 +54,7 @@ static void model_15_init(device_t dev) u8 i; msr_t msr; int msrno; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -92,7 +92,7 @@ static void model_15_init(device_t dev) /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 294814f149..ddea603a6a 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -37,7 +37,7 @@ static void model_16_init(device_t dev) u8 i; msr_t msr; int msrno; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -76,7 +76,7 @@ static void model_16_init(device_t dev) /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 2f0822e4b9..097a88fcef 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -16,7 +16,7 @@ #include #include -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif -- cgit v1.2.3