From 5e8e911b7caee021faff96c4e82a77a42544ea62 Mon Sep 17 00:00:00 2001 From: Fred Reitberger Date: Fri, 4 Nov 2022 09:16:06 -0400 Subject: soc/amd/common/include/gpio_defs.h: Add comment for accuracy The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times slightly. Time PCO Others 1mS 0.915mS 1.220mS 2mS 2.013mS 2.684mS Signed-off-by: Fred Reitberger Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/include/amdblocks/gpio_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 187be51332..718a45cffc 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -113,6 +113,7 @@ #define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT) #define GPIO_TIMEBASE_61uS 0 +/* The next value is only 183uS on Picasso. It is 244uS on Cezanne and later SoCs */ #define GPIO_TIMEBASE_183uS (1 << 4) #define GPIO_TIMEBASE_15560uS (1 << 7) #define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | GPIO_TIMEBASE_15560uS) -- cgit v1.2.3