From 5e33e827083abe332cf404793d33fa2152a95bab Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 7 Jul 2010 21:59:06 +0000 Subject: fix some more warnings Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/model_10xxx/init_cpus.c | 2 +- src/cpu/amd/model_fxx/init_cpus.c | 4 +-- src/include/cpu/amd/multicore.h | 3 +++ src/northbridge/amd/amdk8/amdk8.h | 3 ++- src/northbridge/amd/amdk8/amdk8_f.h | 2 +- src/northbridge/amd/amdk8/amdk8_pre_f.h | 1 - src/northbridge/amd/amdk8/coherent_ht.c | 35 +++++++++++++------------- src/northbridge/amd/amdk8/raminit_f_dqs.c | 4 +++ src/northbridge/amd/amdk8/setup_resource_map.c | 4 ++- src/southbridge/amd/rs780/rs780_gfx.c | 31 +++++++++++------------ src/southbridge/amd/sb600/sb600_smbus.c | 5 ++-- src/southbridge/amd/sb600/sb600_smbus.h | 4 +-- src/southbridge/amd/sb700/sb700.h | 5 ++++ src/southbridge/amd/sb700/sb700_early_setup.c | 4 +-- src/southbridge/amd/sb700/sb700_smbus.c | 4 +-- src/southbridge/amd/sb700/sb700_smbus.h | 2 ++ 16 files changed, 64 insertions(+), 49 deletions(-) diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 43a62256f5..15e9ed4f85 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -244,7 +244,7 @@ static void wait_ap_started(u32 ap_apicid, void *gp) } } -static void wait_all_other_cores_started(u32 bsp_apicid) +void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 printk(BIOS_DEBUG, "started ap apicid: "); diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 3fad4e19e3..23edfa08ae 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -178,12 +178,12 @@ static void wait_ap_started(u32 ap_apicid, void *gp) } } -static void wait_all_aps_started(u32 bsp_apicid) +void wait_all_aps_started(u32 bsp_apicid) { for_each_ap(bsp_apicid, 0, wait_ap_started, (void *)0); } -static void wait_all_other_cores_started(u32 bsp_apicid) +void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 printk(BIOS_DEBUG, "started ap apicid: "); diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h index 47328ef80d..21cb23c9eb 100644 --- a/src/include/cpu/amd/multicore.h +++ b/src/include/cpu/amd/multicore.h @@ -38,6 +38,9 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54); struct device; u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu); +#else +void wait_all_other_cores_started(u32 bsp_apicid); +void wait_all_aps_started(u32 bsp_apicid); #endif #endif /* CPU_AMD_QUADCORE_H */ diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 3f849c0c8a..cc970c5906 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -8,8 +8,9 @@ #include "amdk8_pre_f.h" #endif -#ifndef __ROMCC__ +#ifdef __PRE_RAM__ void showallroutes(int level, device_t dev); +void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base); #endif #endif /* AMDK8_H */ diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h index 283e32e235..769f5980ba 100644 --- a/src/northbridge/amd/amdk8/amdk8_f.h +++ b/src/northbridge/amd/amdk8/amdk8_f.h @@ -1,6 +1,6 @@ #ifndef AMDK8_F_H - #define AMDK8_F_H + /* Definitions of various K8 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 diff --git a/src/northbridge/amd/amdk8/amdk8_pre_f.h b/src/northbridge/amd/amdk8/amdk8_pre_f.h index 95293ee236..dae2d97cd3 100644 --- a/src/northbridge/amd/amdk8/amdk8_pre_f.h +++ b/src/northbridge/amd/amdk8/amdk8_pre_f.h @@ -1,5 +1,4 @@ #ifndef AMDK8_PRE_F_H - #define AMDK8_PRE_F_H /* Definitions of various K8 registers */ diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 293abc7067..ad787caabd 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -206,12 +206,12 @@ static void enable_routing(u8 node) print_spew(" done.\n"); } +#if CONFIG_MAX_PHYSICAL_CPUS > 1 static void fill_row(u8 node, u8 row, u32 value) { pci_write_config32(NODE_HT(node), 0x40+(row<<2), value); } -#if CONFIG_MAX_PHYSICAL_CPUS > 1 static u8 link_to_register(int ldt) { /* @@ -447,28 +447,33 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) } #if CROSS_BAR_47_56 -static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) { +static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) +{ uint32_t val; val = get_row(source, dest); val -= link_connection(source, kickout)<<16; fill_row(source, dest, val); } -static void opt_broadcast_rt_group(const u8 *conn, int num) { +static void opt_broadcast_rt_group(const u8 *conn, int num) +{ int i; for(i=0; i 2 -static int optimize_connection_group(const u8 *opt_conn, int num) { +static int optimize_connection_group(const u8 *opt_conn, int num) +{ int needs_reset = 0; int i; for(i=0; i> 22; wrmsr(TOP_MEM, msr); } +#endif static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) { @@ -1802,6 +1804,7 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit) } +#if CONFIG_MEM_TRAIN_SEQ == 1 static unsigned get_htic_bit(unsigned i, unsigned bit) { uint32_t dword; @@ -1816,6 +1819,7 @@ static void wait_till_sysinfo_in_ram(void) if(get_htic_bit(0, 9)) return; } } +#endif static void set_sysinfo_in_ram(unsigned val) { diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index f7621a421f..8d1052e845 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -1,6 +1,8 @@ +#include "amdk8.h" + #define RES_DEBUG 0 -static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base) +void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base) { int i; #if RES_DEBUG diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c index 753af0079f..7decabdac3 100644 --- a/src/southbridge/amd/rs780/rs780_gfx.c +++ b/src/southbridge/amd/rs780/rs780_gfx.c @@ -96,33 +96,33 @@ typedef struct _MMIORANGE MMIORANGE MMIO[8], CreativeMMIO[8]; +#define CIM_STATUS u32 +#define CIM_SUCCESS 0x00000000 +#define CIM_ERROR 0x80000000 +#define CIM_UNSUPPORTED 0x80000001 +#define CIM_DISABLEPORT 0x80000002 + +#define MMIO_ATTRIB_NP_ONLY 1 +#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 +#define MMIO_ATTRIB_SKIP_ZERO 1<<2 + +#ifdef DONT_TRUST_RESOURCE_ALLOCATION static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO) { int i; - for (i=0; i<8; i++) - { + for (i=0; i<8; i++) { if (pMMIO[i].Limit == 0) return &pMMIO[i]; } return 0; } + static void FreeMMIO(MMIORANGE* pMMIO) { pMMIO->Base = 0; pMMIO->Limit = 0; } -#define CIM_STATUS u32 -#define CIM_SUCCESS 0x00000000 -#define CIM_ERROR 0x80000000 -#define CIM_UNSUPPORTED 0x80000001 -#define CIM_DISABLEPORT 0x80000002 - -#define MMIO_ATTRIB_NP_ONLY 1 -#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 -#define MMIO_ATTRIB_SKIP_ZERO 1<<2 - -#ifdef DONT_TRUST_RESOURCE_ALLOCATION static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) { int i; @@ -584,7 +584,6 @@ static void rs780_internal_gfx_enable(device_t dev) { u32 l_dword; int i; - device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); msr_t sysmem; @@ -617,7 +616,7 @@ static void rs780_internal_gfx_enable(device_t dev) /* LPC DMA Deadlock workaround? */ /* GFX_InitCommon*/ - k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); l_dword = pci_read_config32(k8_f0, 0x68); l_dword &= ~(3 << 21); l_dword |= (1 << 21); @@ -632,7 +631,7 @@ static void rs780_internal_gfx_enable(device_t dev) #if (CONFIG_GFXUMA == 1) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ - k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); for (i = 0; i < 12; i++) { l_dword = pci_read_config32(k8_f2, 0x40 + i * 4); diff --git a/src/southbridge/amd/sb600/sb600_smbus.c b/src/southbridge/amd/sb600/sb600_smbus.c index 9e14930b09..8174ce8d44 100644 --- a/src/southbridge/amd/sb600/sb600_smbus.c +++ b/src/southbridge/amd/sb600/sb600_smbus.c @@ -60,7 +60,7 @@ static int smbus_wait_until_done(u32 smbus_io_base) return -3; /* timeout */ } -static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) { u8 byte; @@ -87,8 +87,7 @@ static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) return byte; } -static int do_smbus_send_byte(u32 smbus_io_base, u32 device, - u8 val) +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; diff --git a/src/southbridge/amd/sb600/sb600_smbus.h b/src/southbridge/amd/sb600/sb600_smbus.h index 0745776144..684d0e62c4 100644 --- a/src/southbridge/amd/sb600/sb600_smbus.h +++ b/src/southbridge/amd/sb600/sb600_smbus.h @@ -20,8 +20,6 @@ #ifndef SB600_SMBUS_H #define SB600_SMBUS_H -//#include - #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 #define SMBHSTCTRL 0x2 @@ -58,6 +56,8 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index 81a358bcb1..bf7b297518 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -49,4 +49,9 @@ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); void sb700_enable(device_t dev); +#ifdef __PRE_RAM__ +void sb700_lpc_port80(void); +void sb700_pci_port80(void); +#endif + #endif /* SB700_H */ diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c index 4315c39545..22f804ac23 100644 --- a/src/southbridge/amd/sb700/sb700_early_setup.c +++ b/src/southbridge/amd/sb700/sb700_early_setup.c @@ -231,7 +231,7 @@ void soft_reset(void) outb(0x06, 0x0cf9); } -static void sb700_pci_port80(void) +void sb700_pci_port80(void) { u8 byte; device_t dev; @@ -276,7 +276,7 @@ static void sb700_pci_port80(void) pci_write_config8(dev, 0x4A, byte); } -static void sb700_lpc_port80(void) +void sb700_lpc_port80(void) { u8 byte; device_t dev; diff --git a/src/southbridge/amd/sb700/sb700_smbus.c b/src/southbridge/amd/sb700/sb700_smbus.c index ec3f94c7bc..65e6912568 100644 --- a/src/southbridge/amd/sb700/sb700_smbus.c +++ b/src/southbridge/amd/sb700/sb700_smbus.c @@ -63,7 +63,7 @@ static int smbus_wait_until_done(u32 smbus_io_base) return -3; /* timeout */ } -static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) { u8 byte; @@ -90,7 +90,7 @@ static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) return byte; } -static int do_smbus_send_byte(u32 smbus_io_base, u32 device, +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; diff --git a/src/southbridge/amd/sb700/sb700_smbus.h b/src/southbridge/amd/sb700/sb700_smbus.h index 6acfa99090..c21a1dc0a2 100644 --- a/src/southbridge/amd/sb700/sb700_smbus.h +++ b/src/southbridge/amd/sb700/sb700_smbus.h @@ -56,6 +56,8 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -- cgit v1.2.3