From 5ddcfe5ec17b4b625e7969157a819e931a68d330 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 29 Jan 2021 22:15:08 +0100 Subject: soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its register Signed-off-by: Felix Held Change-Id: Id9838e2433004686e3ea82724c55066bcee1f019 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50147 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Angel Pons --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 72cc60a165..8d8203516c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -202,10 +202,10 @@ void soc_enable_psp_early(void); #define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */ #define PSP_BAR_ENABLES 0x48 -#define PSP_MAILBOX_BAR_EN 0x10 +#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ +#define PSP_MAILBOX_BAR_EN BIT(4) #define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */ -#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ typedef struct aoac_devs { unsigned int :5; -- cgit v1.2.3