From 57c8143350bf357dd7edc13ddf735084eea53d07 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 25 Jul 2020 07:50:51 +0200 Subject: soc/intel/skylake: Enable LAN depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently LAN gets enabled by the option EnableLan, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableLan setting. Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel --- src/mainboard/51nb/x210/devicetree.cb | 1 - src/mainboard/asrock/h110m/devicetree.cb | 2 -- src/mainboard/facebook/monolith/devicetree.cb | 1 - src/mainboard/google/eve/devicetree.cb | 1 - src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/glados/devicetree.cb | 1 - src/mainboard/google/poppy/variants/atlas/devicetree.cb | 1 - src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nami/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 1 - src/mainboard/google/poppy/variants/rammus/devicetree.cb | 1 - src/mainboard/google/poppy/variants/soraka/devicetree.cb | 1 - src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb | 2 -- src/mainboard/intel/saddlebrook/devicetree.cb | 2 -- src/mainboard/libretrend/lt1000/devicetree.cb | 1 - src/mainboard/protectli/vault_kbl/devicetree.cb | 1 - src/mainboard/purism/librem_skl/devicetree.cb | 1 - src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 1 - src/soc/intel/skylake/chip.c | 5 +++-- src/soc/intel/skylake/chip.h | 1 - 21 files changed, 3 insertions(+), 25 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 398271ea99..69469b911b 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "1" register "SataMode" = "0" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index c185b10143..9b56f429a9 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -125,8 +125,6 @@ chip soc/intel/skylake .voltage_limit = 1520 \ }" - register "EnableLan" = "0" - # USB register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index f9a2b6632d..4b08819628 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -47,7 +47,6 @@ chip soc/intel/skylake register "Cio2Enable" = "0" register "PmTimerDisabled" = "1" register "HeciEnabled" = "0" - register "EnableLan" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 64241f8de9..767c77b907 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 4bd4d33430..250b96d8ff 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -65,7 +65,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 739ecc6977..bbfa79f1b5 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 2634a57931..7c4928d47e 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -42,7 +42,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 67864f4beb..7bbddbdf3a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 1bb88aba64..e9514e0bca 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "EnableAzalia" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 7b0fe60ff8..e9d7dea3c2 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 3d255c1d97..a5c905eed9 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -37,7 +37,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index e669fe5200..32429f9ced 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -42,7 +42,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index ec896ebbe2..2970a2e430 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b5979fc8a8..a8e51950d8 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -50,8 +50,6 @@ chip soc/intel/skylake # RP17, uses uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" - register EnableLan = "1" - # USB related register "SsicPortEnable" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 71102791a6..5a24705206 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -140,8 +140,6 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[12]" = "1" - register "EnableLan" = "1" - # USB related register "SsicPortEnable" = "1" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index b1ffb56d1f..67b56ff830 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 40f0d19029..ef2cfbb9a6 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "EnableAzalia" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 6e24f5a87d..6943505e40 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -45,7 +45,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 9a1ca31f57..8a369b79b9 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -27,7 +27,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 3a9dd5cf44..3267d86eb7 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -242,8 +242,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; - params->PchLanEnable = config->EnableLan; - if (config->EnableLan) { + dev = pcidev_path_on_root(PCH_DEVFN_GBE); + params->PchLanEnable = dev ? dev->enabled : 0; + if (params->PchLanEnable) { params->PchLanLtrEnable = config->EnableLanLtr; params->PchLanK1OffEnable = config->EnableLanK1Off; params->PchLanClkReqSupported = config->LanClkReqSupported; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a9c69cf301..b243bdea75 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -136,7 +136,6 @@ struct soc_intel_skylake_config { u8 CmdTriStateDis; /* Lan */ - u8 EnableLan; u8 EnableLanLtr; u8 EnableLanK1Off; u8 LanClkReqSupported; -- cgit v1.2.3