From 5787a4c53b56325dad364f11774b481fc27a9684 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 5 Mar 2024 21:44:25 +0100 Subject: mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine type Explicitly assign the 'PCIE' value to the 'type' field of the corresponding MPIO chips in the devicetree. Since the mpio_type enum element 'PCIE' has the value 0, this won't change the behavior, but explicitly assigning this makes this easier to understand. Signed-off-by: Felix Held Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/81095 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Varshit Pandya Reviewed-by: Arthur Heymans --- src/mainboard/amd/onyx_poc/devicetree.cb | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index 39c681d1c4..35978479bc 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -57,6 +57,7 @@ chip soc/amd/genoa_poc device ref rcec_0 on end device ref gpp_bridge_0_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P2 + register "type" = "PCIE" register "start_lane" = "48" register "end_lane" = "63" register "gpio_group" = "1" @@ -66,6 +67,7 @@ chip soc/amd/genoa_poc end device ref gpp_bridge_0_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G2 + register "type" = "PCIE" register "start_lane" = "112" register "end_lane" = "127" register "gpio_group" = "1" @@ -76,6 +78,7 @@ chip soc/amd/genoa_poc end device ref gpp_bridge_0_0_c on chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "PCIE" register "start_lane" = "128" register "end_lane" = "131" register "gpio_group" = "1" @@ -98,6 +101,7 @@ chip soc/amd/genoa_poc device ref rcec_1 on end device ref gpp_bridge_1_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P3 + register "type" = "PCIE" register "start_lane" = "16" register "end_lane" = "31" register "gpio_group" = "1" @@ -107,6 +111,7 @@ chip soc/amd/genoa_poc end device ref gpp_bridge_1_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G3 + register "type" = "PCIE" register "start_lane" = "80" register "end_lane" = "95" register "gpio_group" = "1" @@ -121,6 +126,7 @@ chip soc/amd/genoa_poc device ref rcec_2 on end device ref gpp_bridge_2_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P1 + register "type" = "PCIE" register "start_lane" = "32" register "end_lane" = "47" register "gpio_group" = "1" @@ -131,6 +137,7 @@ chip soc/amd/genoa_poc end device ref gpp_bridge_2_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G1 + register "type" = "PCIE" register "start_lane" = "64" register "end_lane" = "79" register "gpio_group" = "1" @@ -146,6 +153,7 @@ chip soc/amd/genoa_poc device ref rcec_3 on end device ref gpp_bridge_3_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P0 + register "type" = "PCIE" register "start_lane" = "0" register "end_lane" = "15" register "gpio_group" = "1" @@ -155,6 +163,7 @@ chip soc/amd/genoa_poc end device ref gpp_bridge_3_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G0 + register "type" = "PCIE" register "start_lane" = "96" register "end_lane" = "111" register "gpio_group" = "1" @@ -164,6 +173,7 @@ chip soc/amd/genoa_poc end device ref gpp_bridge_3_0_c on # WAFL chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "PCIE" register "start_lane" = "132" register "end_lane" = "133" register "gpio_group" = "1" @@ -173,6 +183,7 @@ chip soc/amd/genoa_poc end device ref gpp_bridge_3_1_c on # BMC chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "PCIE" register "start_lane" = "134" register "end_lane" = "134" register "gpio_group" = "1" @@ -183,6 +194,7 @@ chip soc/amd/genoa_poc end device ref gpp_bridge_3_2_c on # BMC chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "PCIE" register "start_lane" = "135" register "end_lane" = "135" register "gpio_group" = "1" -- cgit v1.2.3