From 569887a64084f18da1daf55ff0f10a855bb537c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 17 Oct 2019 16:32:24 +0200 Subject: soc/intel/common: lpc/espi: fix wrong lock bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance with doc#332691-003EN and doc#334819-001. Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Patrick Georgi --- src/soc/intel/common/block/lpc/lpc_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index c066f68f17..9a72580af6 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -37,7 +37,7 @@ #define LPC_LGMR_WINDOW_SIZE (64 * KiB) #define LPC_BIOS_CNTL 0xdc #define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 2) /* LE */ +#define LPC_BC_LE (1 << 1) /* LE */ #define LPC_BC_EISS (1 << 5) /* EISS */ #define LPC_PCCTL 0xE0 /* PCI Clock Control */ #define LPC_PCCTL_CLKRUN_EN (1 << 0) -- cgit v1.2.3