From 550bdc9050eb97d1c4ddc8d6890cd1713d65ca89 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Thu, 28 Oct 2021 18:02:53 +0600 Subject: mb/google/brya/anahera: Disable autonomous GPIO power management With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully. BUG=b:202246591 TEST=FW_NAME=anahera emerge-brya coreboot chromeos-bootimage. Signed-off-by: Wisley Chen Change-Id: I9137b6264ee80bc9e00dfdc3ab3926bccb4bf47c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58695 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/anahera/overridetree.cb | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 0225f6c133..7d003b3f62 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -22,6 +22,17 @@ fw_config end end chip soc/intel/alderlake + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- cgit v1.2.3