From 51605e2c9e21d0aa81a8368ef818b48cd34f3bfd Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 20 Feb 2018 14:37:03 -0800 Subject: soc/intel/cannonlake: Clear EMMC timeout register Clear EMMC timeout register to avoid EMMC issue according to cannonlake bios writer guide. BUG=b.71586766 TEST=Install OS into EMMC successfully on meowth P1 platform. Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/23831 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik --- src/soc/intel/cannonlake/acpi/scs.asl | 10 ++++++++++ src/soc/intel/cannonlake/acpi/southbridge.asl | 6 +++--- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 4d68d56391..4062e704a1 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include + Scope (\_SB.PCI0) { /* EMMC */ Device(PEMC) { @@ -34,6 +36,10 @@ Scope (\_SB.PCI0) { Store(0, PGEN) // Disable PG + /* Clear register 0x1C20/0x4820 */ + ^^PCRA (PID_EMMC, 0x1C20, 0x0) + ^^PCRA (PID_EMMC, 0x4820, 0x0) + /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) @@ -78,6 +84,10 @@ Scope (\_SB.PCI0) { { Store (0, PGEN) /* Disable PG */ + /* Clear register 0x1C20/0x4820 */ + ^^PCRA (PID_SDX, 0x1C20, 0x0) + ^^PCRA (PID_SDX, 0x4820, 0x0) + /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 8d74da9f42..4a62485324 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -19,12 +19,12 @@ /* PCI IRQ assignment */ #include "pci_irqs.asl" -/* eMMC, SD Card */ -#include "scs.asl" - /* PCR access */ #include +/* eMMC, SD Card */ +#include "scs.asl" + /* GPIO controller */ #include "gpio.asl" -- cgit v1.2.3