From 51067116eb8b390e8fc8c8f96c7097a2637e7159 Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Fri, 14 Nov 2014 14:50:47 -0800 Subject: google/rush_ryu: devicetree: Add dsi panel mode settings BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I2bd1b2c2b1bfe75702a12129ca57b3afa6542575 Signed-off-by: Patrick Georgi Original-Commit-Id: 6aac5ecb014ab213f465b9aa78f587994c6b3624 Original-Change-Id: I64f2df49a258b4dd024305a9757704a823265e99 Original-Signed-off-by: Jimmy Zhang Original-Reviewed-on: https://chromium-review.googlesource.com/229911 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Aaron Durbin Reviewed-on: http://review.coreboot.org/9516 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/rush_ryu/devicetree.cb | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/mainboard/google/rush_ryu/devicetree.cb b/src/mainboard/google/rush_ryu/devicetree.cb index 98284fc4e6..c0af141fb6 100644 --- a/src/mainboard/google/rush_ryu/devicetree.cb +++ b/src/mainboard/google/rush_ryu/devicetree.cb @@ -24,4 +24,26 @@ chip soc/nvidia/tegra132 device cpu 0 on end device cpu 1 on end end + + register "display_controller" = "TEGRA_ARM_DISPLAYA" + register "xres" = "2560" + register "yres" = "1800" + + # bits per pixel and color depth + register "framebuffer_bits_per_pixel" = "32" + register "color_depth" = "12" + + register "href_to_sync" = "1" + register "hfront_porch" = "80" + register "hsync_width" = "80" + register "hback_porch" = "80" + + register "vref_to_sync" = "1" + register "vfront_porch" = "4" + register "vsync_width" = "4" + register "vback_porch" = "4" + register "refresh" = "60" + + # kernel driver + register "pixel_clock" = "301620000" end -- cgit v1.2.3