From 4fd80b286b6a868b4f45bad24af0870342d3fcae Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 3 Mar 2022 19:16:04 +0800 Subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 The mainboard may not be able to disable the internal cap, so we want to set 0xe0 for all boards to minimize the internal cap. And a mainboard implementation may choose XTAL with higher cload if the frequency requirement is met, and the total capacitance can be tuned externally for different boards. BUG=b:218439447 TEST=set capid to 0xe0. Signed-off-by: Rex-BC Chen Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8186/rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 2f78be8fa6..7375bc39e6 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -13,7 +13,7 @@ #include #include -#define MT8186_RTC_DXCO_CAPID 0xC0 +#define MT8186_RTC_DXCO_CAPID 0xE0 /* Initialize RTC setting of using DCXO clock */ static bool rtc_enable_dcxo(void) -- cgit v1.2.3