From 4f3d400a30247b7795254517078529d070f4129f Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Sun, 1 Nov 2015 19:55:48 +0000 Subject: imgtec/pistachio: disable default RPU gate register values The RPU Clock register defaults to on for all clocks. This is modified to OFF, and the MIPS clock control modified to ON, by default. This is because the linux kernel will manage the clocks at all times, but the RPU can only disable clocks if the WIFI module has been loaded. Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f Signed-off-by: Ionela Voinescu Reviewed-on: https://review.coreboot.org/12773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/urara/bootblock.c | 8 ++++++++ src/soc/imgtec/pistachio/clocks.c | 12 ++++++++++++ src/soc/imgtec/pistachio/include/soc/clocks.h | 1 + 3 files changed, 21 insertions(+) diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 7775916f11..121f35df14 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -190,6 +190,14 @@ static void bootblock_mainboard_init(void) if (ret != CLOCKS_OK) return; + /* + * Move peripheral clock control from RPU to MIPS. + * The RPU gate register is not managed in Linux so disable its default + * values and assign MIPS gate register the default values. + * *Note*: All unused clocks will be gated by Linux + */ + setup_clk_gate_defaults(); + /* Setup SPIM1 MFIOs */ spim1_mfio_setup(); /* Setup UART1 clock and MFIOs diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index ab316e3f97..9f3da1ad37 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -82,6 +82,12 @@ #define MIPSCLKOUT_CTRL_ADDR 0xB8144208 #define MIPSCLKOUT_MASK 0x000000FF +/* Peripheral Clock gate reg */ +#define MIPS_CLOCK_GATE_ADDR 0xB8144900 +#define RPU_CLOCK_GATE_ADDR 0xB8144904 +#define MIPS_CLOCK_GATE_ALL_ON 0x3fff +#define RPU_CLOCK_GATE_ALL_OFF 0x0 + /* Definitions for USB clock setup */ #define USBPHYCLKOUT_CTRL_ADDR 0xB814422C #define USBPHYCLKOUT_MASK 0X0000003F @@ -499,3 +505,9 @@ void eth_clk_setup(u8 mux, u8 divider) write32(PISTACHIO_CLOCK_SWITCH, reg); } } + +void setup_clk_gate_defaults(void) +{ + write32(MIPS_CLOCK_GATE_ADDR, MIPS_CLOCK_GATE_ALL_ON); + write32(RPU_CLOCK_GATE_ADDR, RPU_CLOCK_GATE_ALL_OFF); +} diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h index fc07f0aa2d..27ba6d6c20 100644 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ b/src/soc/imgtec/pistachio/include/soc/clocks.h @@ -32,6 +32,7 @@ void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface); int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel); void rom_clk_setup(u8 divider); void eth_clk_setup(u8 mux, u8 divider); +void setup_clk_gate_defaults(void); enum { CLOCKS_OK = 0, PLL_TIMEOUT = -1, -- cgit v1.2.3