From 4f2f01a8fa4035c9c4c73dd7add490915ab4b31c Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Sun, 7 Jun 2015 23:07:16 +0100 Subject: pistachio: increase romstage size This change is necessary to support future additions to romstage. Change-Id: Ibb69994847945c7adbafbf2bc677b33821df8146 Signed-off-by: Ionela Voinescu Reviewed-on: http://review.coreboot.org/10457 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 326a26bb79..b36d47e9b6 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -38,8 +38,8 @@ SECTIONS * and then through the identity mapping in ROM stage. */ SRAM_START(0x1a000000) - ROMSTAGE(0x1a005000, 36K) - PRERAM_CBFS_CACHE(0x1a00e000, 72K) + ROMSTAGE(0x1a005000, 40K) + PRERAM_CBFS_CACHE(0x1a00f000, 68K) SRAM_END(0x1a020000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. -- cgit v1.2.3