From 4ebe6dff1a9b2643e739371d3399f25a2c0e68a2 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 28 Feb 2020 16:25:08 -0700 Subject: mb/google/dedede: Add PCIe Root Port Configuration Add configuration for all the PCIe Root ports and Clock Source. Configure the Root Ports as disabled and clock sources as not used. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/dedede/variants/baseboard/devicetree.cb | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d5f58bae3e..0efb76dfe0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -76,6 +76,31 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" + # PCIE Root Port Configuration + register "PcieRpEnable[0]" = "0" + register "PcieRpEnable[1]" = "0" + register "PcieRpEnable[2]" = "0" + register "PcieRpEnable[3]" = "0" + register "PcieRpEnable[4]" = "0" + register "PcieRpEnable[5]" = "0" + register "PcieRpEnable[6]" = "0" + register "PcieRpEnable[7]" = "0" + + register "PcieClkSrcUsage[0]" = "0xff" + register "PcieClkSrcUsage[1]" = "0xff" + register "PcieClkSrcUsage[2]" = "0xff" + register "PcieClkSrcUsage[3]" = "0xff" + register "PcieClkSrcUsage[4]" = "0xff" + register "PcieClkSrcUsage[5]" = "0xff" + + # PCIE Clock Request to Clock Source Mapping + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1" -- cgit v1.2.3