From 4dcac1304356fbc4e7c83d9eb024a0b0bde9f94e Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 12 Jul 2021 16:19:53 +0200 Subject: intel/kblrvp: Move lockdown config to baseboard devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clean up lockdown configuration and move it to the baseboard's devicetree. Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it for the rvp8 variant for consistency as well. Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains identical. intel/rvp8 changes, as expected. Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212 Reviewed-by: Michael Niewöhner Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb | 4 ++++ src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb | 5 ----- src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb | 5 ----- src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb | 5 ----- 4 files changed, 4 insertions(+), 15 deletions(-) diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index e17c8b71f3..a5a51bf397 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -110,6 +110,10 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index fa1367410b..bc4a677138 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -105,11 +105,6 @@ chip soc/intel/skylake .tdp_pl2_override = 60, }" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device domain 0 on device pci 04.0 off end # SA thermal subsystem device pci 17.0 on end # SATA diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 397155b789..b1d291722b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -110,11 +110,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device domain 0 on device pci 05.0 on end # SA IMGU device pci 14.3 on end # Camera diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index b677a343ac..83a86adb37 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -150,11 +150,6 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_G5" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3