From 4c0dc4ee918c3046719af868999785a381f06cc5 Mon Sep 17 00:00:00 2001 From: Hsiao Chien Sung Date: Fri, 31 Mar 2023 12:56:08 +0800 Subject: soc/mediatek/mt8188: Support 4K resolution display The original clock rate 416MHz is insufficient for 4K resolution and causing the screen to glitch. Set the clock rate to 594MHz to support 4K resolution. BUG=b:236328487 TEST=Glitching screen was fixed after applying this patch Change-Id: Ic40dd28264d03ef7218ff4edd8d4182e0fe74ea3 Signed-off-by: Hsiao Chien Sung Signed-off-by: Jason Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/75661 Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8188/pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c index 176b8845fd..d892e1cf72 100644 --- a/src/soc/mediatek/mt8188/pll.c +++ b/src/soc/mediatek/mt8188/pll.c @@ -256,7 +256,7 @@ static const struct mux_sel mux_sels[] = { { .id = TOP_SCP_SEL, .sel = 5 }, /* 5: mainpll_d4_d2 */ { .id = TOP_BUS_AXIMEM_SEL, .sel = 1 }, /* 1: mainpll_d7_d2 */ /* CLK_CFG_1 */ - { .id = TOP_VPP_SEL, .sel = 8 }, /* 8: univpll_d6 */ + { .id = TOP_VPP_SEL, .sel = 11 }, /* 11: tvdpll1_ck */ { .id = TOP_ETHDR_SEL, .sel = 8 }, /* 8: univpll_d6 */ { .id = TOP_IPE_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ { .id = TOP_CAM_SEL, .sel = 9 }, /* 9: mainpll_d4_d2 */ -- cgit v1.2.3