From 4be064a1d8b3693954c637e578cf3d6aec625105 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 8 Dec 2020 17:21:04 +0100 Subject: soc/amd/cezanne: add common SMBus code to build Since the IOAPIC in the FCH gets set up in the SMBus code, also select IOAPIC in Kconfig. Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48474 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/Kconfig | 2 ++ src/soc/amd/cezanne/include/soc/iomap.h | 9 +++++++++ src/soc/amd/cezanne/include/soc/southbridge.h | 8 ++++++++ 3 files changed, 19 insertions(+) create mode 100644 src/soc/amd/cezanne/include/soc/iomap.h create mode 100644 src/soc/amd/cezanne/include/soc/southbridge.h diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index fe248c6097..be45de4145 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,11 +13,13 @@ config SOC_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select IOAPIC select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H config EARLY_RESERVED_DRAM_BASE diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h new file mode 100644 index 0000000000..96313eaf3c --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_IOMAP_H +#define AMD_CEZANNE_IOMAP_H + +/* I/O Ranges */ +#define SMB_BASE_ADDR 0xb00 + +#endif /* AMD_CEZANNE_IOMAP_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h new file mode 100644 index 0000000000..0f26ff0807 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_SOUTHBRIDGE_H +#define AMD_CEZANNE_SOUTHBRIDGE_H + +#include + +#endif /* AMD_CEZANNE_SOUTHBRIDGE_H */ -- cgit v1.2.3