From 4bdb089147b7cfa3ab52de7449e7fba82672a080 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 26 Jun 2024 11:29:24 +0200 Subject: device/azalia_device.c: Always read-write GCAP In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP register is RO (Read Only). However, it is known that in some Intel PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some of the bitfields in the GCAP register are R/WO (Read / Write Once). GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock bit for GCAP elsewhere. Lock GCAP by reading GCAP and writing back the same value. This has no effect on platforms that implement GCAP as a RO register or lock GCAP through a different mechanism. Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/83218 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/device/Kconfig | 9 --------- src/device/azalia_device.c | 17 +++++++++++++---- src/soc/intel/common/block/hda/Kconfig | 1 - 3 files changed, 13 insertions(+), 14 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index f1343f8a5f..243e23e52a 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -575,15 +575,6 @@ config AZALIA_HDA_CODEC_SUPPORT mainboard directory to the build which contain the board-specific HD audio codec configuration. -config AZALIA_LOCK_DOWN_R_WO_GCAP - def_bool n - depends on AZALIA_HDA_CODEC_SUPPORT - help - The GCAP register is implemented as R/WO (Read / Write Once) on some - HD Audio controllers, such as Intel 6-series PCHs. Select this option - to lock down the GCAP register after deasserting the controller reset - bit. Locking is done by reading GCAP and writing back the read value. - config PCIEXP_PLUGIN_SUPPORT bool default y diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 02bbf8944f..4eed48906c 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -56,10 +56,19 @@ static u16 codec_detect(u8 *base) if (azalia_exit_reset(base) < 0) goto no_codec; - if (CONFIG(AZALIA_LOCK_DOWN_R_WO_GCAP)) { - /* If GCAP is R/WO, lock it down after deasserting controller reset */ - write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - } + /* + * In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP + * register is RO (Read Only). However, it is known that in some Intel + * PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some + * of the bitfields in the GCAP register are R/WO (Read / Write Once). + * GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock + * bit for GCAP elsewhere. + * + * Lock GCAP by reading GCAP and writing back the same value. This has + * no effect on platforms that implement GCAP as a RO register or lock + * GCAP through a different mechanism. + */ + write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); /* clear STATESTS bits (BAR + 0x0e)[14:0] */ reg16 = read16(base + HDA_STATESTS_REG); diff --git a/src/soc/intel/common/block/hda/Kconfig b/src/soc/intel/common/block/hda/Kconfig index 64f34ef2ab..a91764a1ef 100644 --- a/src/soc/intel/common/block/hda/Kconfig +++ b/src/soc/intel/common/block/hda/Kconfig @@ -8,6 +8,5 @@ config SOC_INTEL_COMMON_BLOCK_HDA config SOC_INTEL_COMMON_BLOCK_HDA_VERB bool depends on SOC_INTEL_COMMON_BLOCK_HDA - select AZALIA_LOCK_DOWN_R_WO_GCAP help Enable initialization of HDA codecs. -- cgit v1.2.3