From 4af1fe23f8658ec51380b68ecdd317ddc1dfb854 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 24 Aug 2019 23:54:41 -0500 Subject: google/link: fix detection of dimm on channel 1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Changes to the sandybridge memory init code (both MRC and native) now require SPD data on all populated channels in order for dimms to be detected properly, so copy spd_data[0] to spd_data[2], as LINK always has 2 channels of memory down. Test: boot google/link, observe onboard RAM correctly detected on both channels Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Rudolph --- src/mainboard/google/link/romstage.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f3f07cdce..8e8d94335c 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -156,8 +156,12 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(pei_data->spd_data[0], locate_spd(), sizeof(pei_data->spd_data[0])); + memcpy(pei_data->spd_data[2], pei_data->spd_data[0], + sizeof(pei_data->spd_data[0])); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -180,7 +184,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(&spd[0], locate_spd(), 128); + memcpy(&spd[2], &spd[0], 128); } void mainboard_early_init(int s3resume) -- cgit v1.2.3