From 46514c2b877c29c2d7c2061a9785736e270c0c62 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 11 Jun 2020 11:59:07 -0700 Subject: treewide: Add Kconfig variable MEMLAYOUT_LD_FILE This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- Makefile.inc | 8 +++ src/Kconfig | 9 ++++ src/arch/arm/Makefile.inc | 10 ++-- src/arch/arm64/Makefile.inc | 10 ++-- src/arch/ppc64/Makefile.inc | 6 +-- src/arch/riscv/Makefile.inc | 6 +-- src/arch/x86/Kconfig | 4 ++ src/arch/x86/Makefile.inc | 11 ++-- src/cpu/ti/am335x/Kconfig | 8 +++ src/cpu/ti/am335x/Makefile.inc | 5 +- src/mainboard/cavium/cn8100_sff_evb/Makefile.inc | 5 -- src/mainboard/cavium/cn8100_sff_evb/memlayout.ld | 1 - src/mainboard/emulation/qemu-aarch64/Kconfig | 4 ++ src/mainboard/emulation/qemu-aarch64/Makefile.inc | 4 -- src/mainboard/emulation/qemu-armv7/Kconfig | 4 ++ src/mainboard/emulation/qemu-armv7/Makefile.inc | 4 -- src/mainboard/emulation/qemu-power8/Kconfig | 4 ++ src/mainboard/emulation/qemu-power8/Makefile.inc | 4 -- src/mainboard/emulation/qemu-riscv/Kconfig | 4 ++ src/mainboard/emulation/qemu-riscv/Makefile.inc | 4 -- src/mainboard/emulation/spike-riscv/Kconfig | 4 ++ src/mainboard/emulation/spike-riscv/Makefile.inc | 4 -- src/mainboard/google/cheza/Makefile.inc | 4 -- src/mainboard/google/cheza/memlayout.ld | 3 -- src/mainboard/google/daisy/Makefile.inc | 4 -- src/mainboard/google/daisy/memlayout.ld | 3 -- src/mainboard/google/foster/Makefile.inc | 5 -- src/mainboard/google/foster/memlayout.ld | 3 -- src/mainboard/google/gale/Makefile.inc | 5 -- src/mainboard/google/gale/memlayout.ld | 3 -- src/mainboard/google/gru/Makefile.inc | 6 --- src/mainboard/google/gru/memlayout.ld | 3 -- src/mainboard/google/kukui/Makefile.inc | 5 -- src/mainboard/google/kukui/memlayout.ld | 3 -- src/mainboard/google/mistral/Makefile.inc | 4 -- src/mainboard/google/mistral/memlayout.ld | 3 -- src/mainboard/google/nyan/Makefile.inc | 5 -- src/mainboard/google/nyan/memlayout.ld | 3 -- src/mainboard/google/nyan_big/Makefile.inc | 5 -- src/mainboard/google/nyan_big/memlayout.ld | 3 -- src/mainboard/google/nyan_blaze/Makefile.inc | 5 -- src/mainboard/google/nyan_blaze/memlayout.ld | 3 -- src/mainboard/google/oak/Makefile.inc | 4 -- src/mainboard/google/oak/memlayout.ld | 3 -- src/mainboard/google/peach_pit/Makefile.inc | 4 -- src/mainboard/google/peach_pit/memlayout.ld | 3 -- src/mainboard/google/smaug/Makefile.inc | 5 -- src/mainboard/google/smaug/memlayout.ld | 3 -- src/mainboard/google/storm/Makefile.inc | 5 -- src/mainboard/google/storm/memlayout.ld | 3 -- src/mainboard/google/trogdor/Makefile.inc | 4 -- src/mainboard/google/trogdor/memlayout.ld | 3 -- src/mainboard/google/veyron/Makefile.inc | 5 -- src/mainboard/google/veyron/memlayout.ld | 3 -- src/mainboard/google/veyron_mickey/Makefile.inc | 5 -- src/mainboard/google/veyron_mickey/memlayout.ld | 3 -- src/mainboard/google/veyron_rialto/Makefile.inc | 5 -- src/mainboard/google/veyron_rialto/memlayout.ld | 3 -- src/mainboard/google/zork/Makefile.inc | 1 - src/mainboard/opencellular/elgon/Makefile.inc | 4 -- src/mainboard/opencellular/elgon/memlayout.ld | 1 - src/mainboard/sifive/hifive-unleashed/Makefile.inc | 4 -- src/mainboard/sifive/hifive-unleashed/memlayout.ld | 3 -- src/mainboard/ti/beaglebone/Makefile.inc | 4 -- src/mainboard/ti/beaglebone/memlayout.ld | 1 - src/soc/cavium/cn81xx/Kconfig | 4 ++ src/soc/cavium/cn81xx/include/soc/memlayout.ld | 39 -------------- src/soc/cavium/cn81xx/memlayout.ld | 39 ++++++++++++++ src/soc/mediatek/mt8173/Kconfig | 4 ++ src/soc/mediatek/mt8173/include/soc/memlayout.ld | 45 ---------------- src/soc/mediatek/mt8173/memlayout.ld | 45 ++++++++++++++++ src/soc/mediatek/mt8183/Kconfig | 4 ++ src/soc/mediatek/mt8183/include/soc/memlayout.ld | 43 --------------- src/soc/mediatek/mt8183/memlayout.ld | 43 +++++++++++++++ src/soc/nvidia/tegra124/Kconfig | 4 ++ src/soc/nvidia/tegra124/include/soc/memlayout.ld | 33 ------------ src/soc/nvidia/tegra124/memlayout.ld | 33 ++++++++++++ src/soc/nvidia/tegra210/Kconfig | 4 ++ src/soc/nvidia/tegra210/include/soc/memlayout.ld | 37 ------------- src/soc/nvidia/tegra210/memlayout.ld | 37 +++++++++++++ src/soc/qualcomm/ipq40xx/Kconfig | 4 ++ src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld | 51 ------------------ src/soc/qualcomm/ipq40xx/memlayout.ld | 51 ++++++++++++++++++ src/soc/qualcomm/ipq806x/Kconfig | 4 ++ src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 38 ------------- src/soc/qualcomm/ipq806x/memlayout.ld | 38 +++++++++++++ src/soc/qualcomm/qcs405/Kconfig | 4 ++ src/soc/qualcomm/qcs405/include/soc/memlayout.ld | 38 ------------- src/soc/qualcomm/qcs405/memlayout.ld | 38 +++++++++++++ src/soc/qualcomm/sc7180/Kconfig | 4 ++ src/soc/qualcomm/sc7180/include/soc/memlayout.ld | 56 ------------------- src/soc/qualcomm/sc7180/memlayout.ld | 56 +++++++++++++++++++ src/soc/qualcomm/sdm845/Kconfig | 4 ++ src/soc/qualcomm/sdm845/include/soc/memlayout.ld | 63 ---------------------- src/soc/qualcomm/sdm845/memlayout.ld | 63 ++++++++++++++++++++++ src/soc/rockchip/rk3288/Kconfig | 4 ++ src/soc/rockchip/rk3288/include/soc/memlayout.ld | 35 ------------ src/soc/rockchip/rk3288/memlayout.ld | 35 ++++++++++++ src/soc/rockchip/rk3399/Kconfig | 4 ++ src/soc/rockchip/rk3399/include/soc/memlayout.ld | 35 ------------ src/soc/rockchip/rk3399/memlayout.ld | 35 ++++++++++++ src/soc/samsung/exynos5250/Kconfig | 4 ++ .../samsung/exynos5250/include/soc/memlayout.ld | 32 ----------- src/soc/samsung/exynos5250/memlayout.ld | 32 +++++++++++ src/soc/samsung/exynos5420/Kconfig | 4 ++ .../samsung/exynos5420/include/soc/memlayout.ld | 33 ------------ src/soc/samsung/exynos5420/memlayout.ld | 33 ++++++++++++ src/soc/sifive/fu540/Kconfig | 4 ++ src/soc/sifive/fu540/include/soc/memlayout.ld | 27 ---------- src/soc/sifive/fu540/memlayout.ld | 27 ++++++++++ 110 files changed, 735 insertions(+), 815 deletions(-) delete mode 100644 src/mainboard/cavium/cn8100_sff_evb/memlayout.ld delete mode 100644 src/mainboard/google/cheza/memlayout.ld delete mode 100644 src/mainboard/google/daisy/memlayout.ld delete mode 100644 src/mainboard/google/foster/memlayout.ld delete mode 100644 src/mainboard/google/gale/memlayout.ld delete mode 100644 src/mainboard/google/gru/memlayout.ld delete mode 100644 src/mainboard/google/kukui/memlayout.ld delete mode 100644 src/mainboard/google/mistral/memlayout.ld delete mode 100644 src/mainboard/google/nyan/memlayout.ld delete mode 100644 src/mainboard/google/nyan_big/memlayout.ld delete mode 100644 src/mainboard/google/nyan_blaze/memlayout.ld delete mode 100644 src/mainboard/google/oak/memlayout.ld delete mode 100644 src/mainboard/google/peach_pit/memlayout.ld delete mode 100644 src/mainboard/google/smaug/memlayout.ld delete mode 100644 src/mainboard/google/storm/memlayout.ld delete mode 100644 src/mainboard/google/trogdor/memlayout.ld delete mode 100644 src/mainboard/google/veyron/memlayout.ld delete mode 100644 src/mainboard/google/veyron_mickey/memlayout.ld delete mode 100644 src/mainboard/google/veyron_rialto/memlayout.ld delete mode 100644 src/mainboard/opencellular/elgon/memlayout.ld delete mode 100644 src/mainboard/sifive/hifive-unleashed/memlayout.ld delete mode 100644 src/mainboard/ti/beaglebone/memlayout.ld delete mode 100644 src/soc/cavium/cn81xx/include/soc/memlayout.ld create mode 100644 src/soc/cavium/cn81xx/memlayout.ld delete mode 100644 src/soc/mediatek/mt8173/include/soc/memlayout.ld create mode 100644 src/soc/mediatek/mt8173/memlayout.ld delete mode 100644 src/soc/mediatek/mt8183/include/soc/memlayout.ld create mode 100644 src/soc/mediatek/mt8183/memlayout.ld delete mode 100644 src/soc/nvidia/tegra124/include/soc/memlayout.ld create mode 100644 src/soc/nvidia/tegra124/memlayout.ld delete mode 100644 src/soc/nvidia/tegra210/include/soc/memlayout.ld create mode 100644 src/soc/nvidia/tegra210/memlayout.ld delete mode 100644 src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld create mode 100644 src/soc/qualcomm/ipq40xx/memlayout.ld delete mode 100644 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld create mode 100644 src/soc/qualcomm/ipq806x/memlayout.ld delete mode 100644 src/soc/qualcomm/qcs405/include/soc/memlayout.ld create mode 100644 src/soc/qualcomm/qcs405/memlayout.ld delete mode 100644 src/soc/qualcomm/sc7180/include/soc/memlayout.ld create mode 100644 src/soc/qualcomm/sc7180/memlayout.ld delete mode 100644 src/soc/qualcomm/sdm845/include/soc/memlayout.ld create mode 100644 src/soc/qualcomm/sdm845/memlayout.ld delete mode 100644 src/soc/rockchip/rk3288/include/soc/memlayout.ld create mode 100644 src/soc/rockchip/rk3288/memlayout.ld delete mode 100644 src/soc/rockchip/rk3399/include/soc/memlayout.ld create mode 100644 src/soc/rockchip/rk3399/memlayout.ld delete mode 100644 src/soc/samsung/exynos5250/include/soc/memlayout.ld create mode 100644 src/soc/samsung/exynos5250/memlayout.ld delete mode 100644 src/soc/samsung/exynos5420/include/soc/memlayout.ld create mode 100644 src/soc/samsung/exynos5420/memlayout.ld delete mode 100644 src/soc/sifive/fu540/include/soc/memlayout.ld create mode 100644 src/soc/sifive/fu540/memlayout.ld diff --git a/Makefile.inc b/Makefile.inc index 86467a66a8..fca7ebdedd 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -13,6 +13,7 @@ CONFIG_CBFS_PREFIX:=$(call strip_quotes,$(CONFIG_CBFS_PREFIX)) CONFIG_FMDFILE:=$(call strip_quotes,$(CONFIG_FMDFILE)) CONFIG_DEVICETREE:=$(call strip_quotes, $(CONFIG_DEVICETREE)) CONFIG_OVERRIDE_DEVICETREE:=$(call strip_quotes, $(CONFIG_OVERRIDE_DEVICETREE)) +CONFIG_MEMLAYOUT_LD_FILE:=$(call strip_quotes, $(CONFIG_MEMLAYOUT_LD_FILE)) ####################################################################### # misleadingly named, this is the coreboot version @@ -609,6 +610,13 @@ smm-c-deps+=$(DEVICETREE_STATIC_C) .PHONY: devicetree devicetree: $(DEVICETREE_STATIC_C) +ramstage-y += $(CONFIG_MEMLAYOUT_LD_FILE) +romstage-y += $(CONFIG_MEMLAYOUT_LD_FILE) +bootblock-y += $(CONFIG_MEMLAYOUT_LD_FILE) +verstage-y += $(CONFIG_MEMLAYOUT_LD_FILE) +postcar-y += $(CONFIG_MEMLAYOUT_LD_FILE) +decompressor-y += $(CONFIG_MEMLAYOUT_LD_FILE) + ####################################################################### # Clean up rules clean-abuild: diff --git a/src/Kconfig b/src/Kconfig index f3d86f2b6d..eef7a96f71 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1182,6 +1182,15 @@ config BOOTBLOCK_CUSTOM # src/lib/bootblock.c#main() C entry point. bool +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/memlayout.ld" + help + This variable allows SoC/mainboard to supply in a custom linker file + if required. This determines the linker file used for all the stages + (bootblock, romstage, verstage, ramstage, postcar) in + src/arch/${ARCH}/Makefile.inc. + ############################################################################### # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 66bf9c4f31..eef2650685 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -50,11 +50,11 @@ bootblock-y += stages.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,bootblock,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group $(objcbfs)/decompressor.debug: $$(decompressor-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,decompressor,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(decompressor-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,decompressor,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(decompressor-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -66,7 +66,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) $(objcbfs)/verstage.debug: $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(call src-to-obj,verstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) --end-group + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(call src-to-obj,verstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) --end-group verstage-y += boot.c verstage-y += div0.c @@ -99,7 +99,7 @@ rmodules_arm-y += eabi_compat.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_ARM @@ -128,6 +128,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 5fd316aa7b..920ff5db51 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -45,11 +45,11 @@ bootblock-y += memmove.S $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(call src-to-obj,bootblock,$(CONFIG_MEMLAYOUT_LD_FILE)) $(objcbfs)/decompressor.debug: $$(decompressor-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(decompressor-objs)) --end-group -T $(call src-to-obj,decompressor,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(decompressor-objs)) --end-group -T $(call src-to-obj,decompressor,$(CONFIG_MEMLAYOUT_LD_FILE)) endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -61,7 +61,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) $(objcbfs)/verstage.debug: $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) --end-group -T $(call src-to-obj,verstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) --end-group -T $(call src-to-obj,verstage,$(CONFIG_MEMLAYOUT_LD_FILE)) verstage-y += boot.c verstage-y += div0.c @@ -99,7 +99,7 @@ rmodules_arm64-y += eabi_compat.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(call src-to-obj,romstage,$(CONFIG_MEMLAYOUT_LD_FILE)) endif # CONFIG_ARCH_ROMSTAGE_ARM64 @@ -134,7 +134,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) # Build ARM Trusted Firmware (BL31) diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index f1a2487a57..d1774a1d15 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -24,7 +24,7 @@ bootblock-generic-ccopts += $(ppc64_flags) $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ + -T $(call src-to-obj,bootblock,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) endif @@ -50,7 +50,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) romstage-c-ccopts += $(ppc64_flags) romstage-S-ccopts += $(ppc64_asm_flags) @@ -83,7 +83,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) ramstage-c-ccopts += $(ppc64_flags) ramstage-S-ccopts += $(ppc64_asm_flags) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 632e220410..cd94692c02 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -64,7 +64,7 @@ bootblock-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ + -T $(call src-to-obj,bootblock,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) bootblock-c-ccopts += $(riscv_flags) @@ -99,7 +99,7 @@ romstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) @@ -148,7 +148,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0a207e19b0..18c1ed3d9f 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -316,4 +316,8 @@ config MAX_ACPI_TABLE_SIZE_KB help Set the maximum size of all ACPI tables in KiB. +config MEMLAYOUT_LD_FILE + string + default "src/arch/x86/memlayout.ld" + endif diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8d4c45714d..1b70fec582 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -67,14 +67,13 @@ endef define early_x86_stage # $1 stage name # $2 oformat -$(1)-y += memlayout.ld # The '.' include path is needed for the generated assembly.inc file. $(1)-S-ccopts += -I. $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) @printf " LINK $$(subst $$(obj)/,,$$(@))\n" - $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $(call src-to-obj,$(1),$(dir)/memlayout.ld) --oformat $(2) + $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $(call src-to-obj,$(1),$(CONFIG_MEMLAYOUT_LD_FILE)) --oformat $(2) -LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section .illegal_globals $$(@) $$(objcbfs)/$(1)_null.offenders >/dev/null 2>&1 if [ -z "$$$$($$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders 2>&1 | grep 'no symbols')" ];then \ echo "Forbidden global variables in $(1):"; \ @@ -201,7 +200,6 @@ postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S postcar-y += memmove.c -postcar-y += memlayout.ld postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c @@ -210,7 +208,7 @@ LDFLAGS_postcar += -Map $(objcbfs)/postcar.map $(objcbfs)/postcar.debug: $$(postcar-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) + $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,$(CONFIG_MEMLAYOUT_LD_FILE)) $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ @@ -236,7 +234,6 @@ ramstage-y += exception.c ramstage-y += idt.S ramstage-y += gdt.c ramstage-$(CONFIG_IOAPIC) += ioapic.c -ramstage-y += memlayout.ld ramstage-y += memmove.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c @@ -289,9 +286,9 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod endif -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) + $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index 6de5eb4df3..3684480929 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -8,3 +8,11 @@ config CPU_TI_AM335X select BOOT_DEVICE_NOT_SPI_FLASH bool default n + +if CPU_TI_AM335X + +config MEMLAYOUT_LD_FILE + string + default "src/cpu/ti/am335x/memlayout.ld" + +endif diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index e1a3b9c7b9..6f414bcf79 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -49,8 +49,5 @@ $(obj)/MLO: $(obj)/coreboot.rom $(obj)/omap-header.bin omap-header-y += header.c -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld -omap-header-y += memlayout.ld +omap-header-srcs += $(CONFIG_MEMLAYOUT_LD_FILE) omap-header-y += header.ld diff --git a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc index c73bc334c4..bd2ea797d7 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc +++ b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc @@ -1,18 +1,13 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-y += memlayout.ld -romstage-y += memlayout.ld romstage-y += romstage.c romstage-y += bdk_devicetree.c ramstage-y += mainboard.c -ramstage-y += memlayout.ld ramstage-y += bdk_devicetree.c -verstage-y += memlayout.ld - MB_DIR = src/mainboard/$(MAINBOARDDIR) LINUX_DTB = sff8104-linux.dtb diff --git a/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld b/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld deleted file mode 100644 index 9349362cfa..0000000000 --- a/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld +++ /dev/null @@ -1 +0,0 @@ - #include diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index b8896d28d1..368f7f3a69 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -24,6 +24,10 @@ config BOARD_SPECIFIC_OPTIONS select MISSING_BOARD_RESET select ARM64_USE_ARM_TRUSTED_FIRMWARE +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/emulation/qemu-aarch64/memlayout.ld" + config MAINBOARD_DIR string default "emulation/qemu-aarch64" diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc index 754656ffa2..15572ca9bc 100644 --- a/src/mainboard/emulation/qemu-aarch64/Makefile.inc +++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc @@ -12,10 +12,6 @@ bootblock-y += mmio.c romstage-y += mmio.c ramstage-y += mmio.c -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld - bootblock-y += bootblock_custom.S CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 4af58434bc..64e5bb7168 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -25,6 +25,10 @@ config BOARD_SPECIFIC_OPTIONS select MISSING_BOARD_RESET select NO_MONOTONIC_TIMER +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/emulation/qemu-armv7/memlayout.ld" + config MAINBOARD_DIR string default "emulation/qemu-armv7" diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index 1b9e997ce1..65fdfe131e 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -15,7 +15,3 @@ ramstage-y += timer.c bootblock-y += mmio.c romstage-y += mmio.c ramstage-y += mmio.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig index aa3aceb367..5dbea721d1 100644 --- a/src/mainboard/emulation/qemu-power8/Kconfig +++ b/src/mainboard/emulation/qemu-power8/Kconfig @@ -17,6 +17,10 @@ config BOARD_SPECIFIC_OPTIONS select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/emulation/qemu-power8/memlayout.ld" + config MAINBOARD_DIR string default "emulation/qemu-power8" diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc index b713df71c9..4011983923 100644 --- a/src/mainboard/emulation/qemu-power8/Makefile.inc +++ b/src/mainboard/emulation/qemu-power8/Makefile.inc @@ -7,7 +7,3 @@ romstage-y += romstage.c ramstage-y += timer.c romstage-y += uart.c ramstage-y += uart.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 66aa599864..5b556fc190 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -30,6 +30,10 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_UART_8250MEM select RISCV_HAS_OPENSBI +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/emulation/qemu-riscv/memlayout.ld" + config MAINBOARD_DIR string default "emulation/qemu-riscv" diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 7ca7e5930c..1a8342d2ca 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -13,8 +13,4 @@ ramstage-y += uart.c ramstage-y += rom_media.c ramstage-y += clint.c -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld - CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig index c46a04781c..3c1ae122e0 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv/Kconfig @@ -11,6 +11,10 @@ config BOARD_SPECIFIC_OPTIONS select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/emulation/spike-riscv/memlayout.ld" + config MAINBOARD_DIR string default "emulation/spike-riscv" diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index 6d2911662d..fc5a7b32d0 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -10,7 +10,3 @@ romstage-y += clint.c ramstage-y += uart.c ramstage-y += rom_media.c ramstage-y += clint.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc index e54aefb0e1..949d775624 100644 --- a/src/mainboard/google/cheza/Makefile.inc +++ b/src/mainboard/google/cheza/Makefile.inc @@ -1,24 +1,20 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += boardid.c -bootblock-y += memlayout.ld bootblock-y += chromeos.c bootblock-y += bootblock.c bootblock-y += reset.c verstage-y += boardid.c -verstage-y += memlayout.ld verstage-y += chromeos.c verstage-y += reset.c romstage-y += boardid.c -romstage-y += memlayout.ld romstage-y += chromeos.c romstage-y += romstage.c romstage-y += reset.c ramstage-y += boardid.c -ramstage-y += memlayout.ld ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/cheza/memlayout.ld b/src/mainboard/google/cheza/memlayout.ld deleted file mode 100644 index 936c1a3e0a..0000000000 --- a/src/mainboard/google/cheza/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - #include diff --git a/src/mainboard/google/daisy/Makefile.inc b/src/mainboard/google/daisy/Makefile.inc index 9faa2e09ef..4f5f87be89 100644 --- a/src/mainboard/google/daisy/Makefile.inc +++ b/src/mainboard/google/daisy/Makefile.inc @@ -9,7 +9,3 @@ romstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += chromeos.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/daisy/memlayout.ld b/src/mainboard/google/daisy/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/daisy/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc index 1b576a9512..7deae3e009 100644 --- a/src/mainboard/google/foster/Makefile.inc +++ b/src/mainboard/google/foster/Makefile.inc @@ -27,8 +27,3 @@ ramstage-y += mainboard.c ramstage-y += reset.c ramstage-y += chromeos.c ramstage-y += sdram_configs.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld -verstage-y += memlayout.ld diff --git a/src/mainboard/google/foster/memlayout.ld b/src/mainboard/google/foster/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/foster/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/gale/Makefile.inc b/src/mainboard/google/gale/Makefile.inc index 84b41e6ebf..f23f804de5 100644 --- a/src/mainboard/google/gale/Makefile.inc +++ b/src/mainboard/google/gale/Makefile.inc @@ -9,7 +9,6 @@ verstage-y += boardid.c verstage-y += cdp.c verstage-y += chromeos.c verstage-y += blsp.c -verstage-y += memlayout.ld verstage-y += reset.c verstage-y += verstage.c @@ -28,7 +27,3 @@ ramstage-y += mainboard.c ramstage-y += mmu.c ramstage-y += reset.c ramstage-y += blsp.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/gale/memlayout.ld b/src/mainboard/google/gale/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/gale/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index 8849162ce0..b800945466 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -2,22 +2,17 @@ subdirs-y += sdram_params/ -decompressor-y += memlayout.ld - bootblock-y += bootblock.c bootblock-y += chromeos.c -bootblock-y += memlayout.ld bootblock-y += pwm_regulator.c bootblock-y += boardid.c bootblock-y += reset.c verstage-y += chromeos.c -verstage-y += memlayout.ld verstage-y += reset.c romstage-y += boardid.c romstage-y += chromeos.c -romstage-y += memlayout.ld romstage-y += pwm_regulator.c romstage-y += romstage.c romstage-y += reset.c @@ -26,6 +21,5 @@ romstage-y += sdram_configs.c ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c -ramstage-y += memlayout.ld ramstage-y += reset.c ramstage-y += sdram_configs.c # Needed for ram_code() diff --git a/src/mainboard/google/gru/memlayout.ld b/src/mainboard/google/gru/memlayout.ld deleted file mode 100644 index 936c1a3e0a..0000000000 --- a/src/mainboard/google/gru/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - #include diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a2a147c399..532712a6c1 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -3,20 +3,16 @@ subdirs-y += panel_params/ bootblock-y += boardid.c bootblock-y += bootblock.c -bootblock-y += memlayout.ld bootblock-y += reset.c -decompressor-y += memlayout.ld verstage-y += chromeos.c verstage-y += early_init.c verstage-y += reset.c verstage-y += verstage.c -verstage-y += memlayout.ld romstage-y += boardid.c romstage-y += chromeos.c romstage-y += early_init.c -romstage-y += memlayout.ld romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c @@ -24,7 +20,6 @@ romstage-y += sdram_configs.c ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c -ramstage-y += memlayout.ld ramstage-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel_flapjack.c ramstage-$(CONFIG_BOARD_GOOGLE_KAKADU) += panel_kakadu.c ramstage-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel_kodama.c diff --git a/src/mainboard/google/kukui/memlayout.ld b/src/mainboard/google/kukui/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/kukui/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index ca191d147e..48faadf2e8 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -1,20 +1,16 @@ -bootblock-y += memlayout.ld bootblock-y += chromeos.c bootblock-y += reset.c bootblock-y += bootblock.c -verstage-y += memlayout.ld verstage-y += chromeos.c verstage-y += reset.c verstage-y += verstage.c -romstage-y += memlayout.ld romstage-y += chromeos.c romstage-y += reset.c romstage-y += romstage.c -ramstage-y += memlayout.ld ramstage-y += chromeos.c ramstage-y += reset.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/mistral/memlayout.ld b/src/mainboard/google/mistral/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/mistral/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index 124d4121d7..190cfc5127 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -29,8 +29,3 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += reset.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += early_configs.c - -bootblock-y += memlayout.ld -verstage-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/nyan/memlayout.ld b/src/mainboard/google/nyan/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/nyan/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index 5cf7356ec1..b734b5ba19 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -28,8 +28,3 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += reset.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += early_configs.c - -bootblock-y += memlayout.ld -verstage-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/nyan_big/memlayout.ld b/src/mainboard/google/nyan_big/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/nyan_big/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index de582badda..54410f0812 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -28,8 +28,3 @@ ramstage-y += reset.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c - -bootblock-y += memlayout.ld -verstage-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/nyan_blaze/memlayout.ld b/src/mainboard/google/nyan_blaze/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/nyan_blaze/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc index 63ccc1e335..79a80ee6c1 100644 --- a/src/mainboard/google/oak/Makefile.inc +++ b/src/mainboard/google/oak/Makefile.inc @@ -1,23 +1,19 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-y += memlayout.ld bootblock-y += chromeos.c bootblock-y += boardid.c bootblock-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c verstage-y += chromeos.c -verstage-y += memlayout.ld verstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c romstage-y += chromeos.c romstage-y += romstage.c sdram_configs.c -romstage-y += memlayout.ld romstage-y += boardid.c romstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c ramstage-y += mainboard.c ramstage-y += chromeos.c -ramstage-y += memlayout.ld ramstage-y += boardid.c ramstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c diff --git a/src/mainboard/google/oak/memlayout.ld b/src/mainboard/google/oak/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/oak/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/peach_pit/Makefile.inc b/src/mainboard/google/peach_pit/Makefile.inc index 9faa2e09ef..4f5f87be89 100644 --- a/src/mainboard/google/peach_pit/Makefile.inc +++ b/src/mainboard/google/peach_pit/Makefile.inc @@ -9,7 +9,3 @@ romstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += chromeos.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/peach_pit/memlayout.ld b/src/mainboard/google/peach_pit/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/peach_pit/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/smaug/Makefile.inc b/src/mainboard/google/smaug/Makefile.inc index 342e0dd35f..32c66b9fca 100644 --- a/src/mainboard/google/smaug/Makefile.inc +++ b/src/mainboard/google/smaug/Makefile.inc @@ -29,8 +29,3 @@ ramstage-y += mainboard.c ramstage-y += reset.c ramstage-y += pmic.c ramstage-y += sdram_configs.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld -verstage-y += memlayout.ld diff --git a/src/mainboard/google/smaug/memlayout.ld b/src/mainboard/google/smaug/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/smaug/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc index 272c49b602..b1bcacd5b5 100644 --- a/src/mainboard/google/storm/Makefile.inc +++ b/src/mainboard/google/storm/Makefile.inc @@ -9,7 +9,6 @@ verstage-y += boardid.c verstage-y += cdp.c verstage-y += chromeos.c verstage-y += gsbi.c -verstage-y += memlayout.ld verstage-y += reset.c romstage-y += romstage.c @@ -26,7 +25,3 @@ ramstage-y += mainboard.c ramstage-y += mmu.c ramstage-y += reset.c ramstage-y += gsbi.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/storm/memlayout.ld b/src/mainboard/google/storm/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/storm/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/trogdor/Makefile.inc b/src/mainboard/google/trogdor/Makefile.inc index 4a2b5d47c6..9a71ea5197 100644 --- a/src/mainboard/google/trogdor/Makefile.inc +++ b/src/mainboard/google/trogdor/Makefile.inc @@ -1,23 +1,19 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += memlayout.ld bootblock-y += boardid.c bootblock-y += chromeos.c bootblock-y += bootblock.c -verstage-y += memlayout.ld ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y) verstage-y += reset.c endif verstage-y += boardid.c verstage-y += chromeos.c -romstage-y += memlayout.ld romstage-y += romstage.c romstage-y += boardid.c romstage-y += chromeos.c -ramstage-y += memlayout.ld ramstage-y += mainboard.c ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y) ramstage-y += reset.c diff --git a/src/mainboard/google/trogdor/memlayout.ld b/src/mainboard/google/trogdor/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/trogdor/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc index 76d141fa27..6c3b7f4c51 100644 --- a/src/mainboard/google/veyron/Makefile.inc +++ b/src/mainboard/google/veyron/Makefile.inc @@ -19,8 +19,3 @@ ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c - -bootblock-y += memlayout.ld -verstage-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/veyron/memlayout.ld b/src/mainboard/google/veyron/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/veyron/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/veyron_mickey/Makefile.inc b/src/mainboard/google/veyron_mickey/Makefile.inc index 76d141fa27..6c3b7f4c51 100644 --- a/src/mainboard/google/veyron_mickey/Makefile.inc +++ b/src/mainboard/google/veyron_mickey/Makefile.inc @@ -19,8 +19,3 @@ ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c - -bootblock-y += memlayout.ld -verstage-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/veyron_mickey/memlayout.ld b/src/mainboard/google/veyron_mickey/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/veyron_mickey/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/veyron_rialto/Makefile.inc b/src/mainboard/google/veyron_rialto/Makefile.inc index 76d141fa27..6c3b7f4c51 100644 --- a/src/mainboard/google/veyron_rialto/Makefile.inc +++ b/src/mainboard/google/veyron_rialto/Makefile.inc @@ -19,8 +19,3 @@ ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c - -bootblock-y += memlayout.ld -verstage-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/veyron_rialto/memlayout.ld b/src/mainboard/google/veyron_rialto/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/google/veyron_rialto/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index 07628c186b..ac828e2765 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -11,7 +11,6 @@ ramstage-y += ec.c ramstage-y += sku_id.c ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -verstage-y += memlayout.ld verstage-y += verstage.c else verstage-y += chromeos.c diff --git a/src/mainboard/opencellular/elgon/Makefile.inc b/src/mainboard/opencellular/elgon/Makefile.inc index 6b019825ab..c938289db8 100644 --- a/src/mainboard/opencellular/elgon/Makefile.inc +++ b/src/mainboard/opencellular/elgon/Makefile.inc @@ -1,18 +1,14 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-y += memlayout.ld bootblock-y += death.c -romstage-y += memlayout.ld romstage-y += romstage.c romstage-y += bdk_devicetree.c romstage-y += death.c ramstage-y += mainboard.c -ramstage-y += memlayout.ld ramstage-y += bdk_devicetree.c ramstage-y += death.c -verstage-y += memlayout.ld verstage-y += death.c diff --git a/src/mainboard/opencellular/elgon/memlayout.ld b/src/mainboard/opencellular/elgon/memlayout.ld deleted file mode 100644 index 9349362cfa..0000000000 --- a/src/mainboard/opencellular/elgon/memlayout.ld +++ /dev/null @@ -1 +0,0 @@ - #include diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 02b8046030..2a32df8756 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -1,17 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only -bootblock-y += memlayout.ld bootblock-y += media.c -romstage-y += memlayout.ld romstage-y += romstage.c romstage-y += media.c -ramstage-y += memlayout.ld ramstage-y += fixup_fdt.c ramstage-y += media.c - DTB=$(obj)/hifive-unleashed.dtb DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts $(DTB): $(DTS) diff --git a/src/mainboard/sifive/hifive-unleashed/memlayout.ld b/src/mainboard/sifive/hifive-unleashed/memlayout.ld deleted file mode 100644 index 0f1fcec9a0..0000000000 --- a/src/mainboard/sifive/hifive-unleashed/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/ti/beaglebone/Makefile.inc b/src/mainboard/ti/beaglebone/Makefile.inc index cf3fc5d79a..a703939f01 100644 --- a/src/mainboard/ti/beaglebone/Makefile.inc +++ b/src/mainboard/ti/beaglebone/Makefile.inc @@ -5,7 +5,3 @@ bootblock-y += leds.c romstage-y += romstage.c #ramstage-y += ramstage.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/ti/beaglebone/memlayout.ld b/src/mainboard/ti/beaglebone/memlayout.ld deleted file mode 100644 index ff79e70ed5..0000000000 --- a/src/mainboard/ti/beaglebone/memlayout.ld +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index f64350eb9e..87edf45cde 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -14,6 +14,10 @@ config SOC_CAVIUM_CN81XX if SOC_CAVIUM_CN81XX +config MEMLAYOUT_LD_FILE + string + default "src/soc/cavium/cn81xx/memlayout.ld" + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld deleted file mode 100644 index 79673c9974..0000000000 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -SECTIONS -{ - DRAM_START(0x00000000) - /* Secure region 0 - 1MiB */ - BL31(0, 0xe0000) - REGION(sff8104, 0xe0000, 0x20000, 0x1000) - - /* Insecure region 1MiB - TOP OF DRAM */ - /* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */ - SRAM_START(BOOTROM_OFFSET) - - STACK(BOOTROM_OFFSET, 16K) - TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) - PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) - FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) - PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) - VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) - TPM_TCPA_LOG(BOOTROM_OFFSET + 0x33000, 2K) - VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) - ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) - - SRAM_END(BOOTROM_OFFSET + 0x80000) - - TTB(BOOTROM_OFFSET + 0x80000, 512K) - RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) - /* Stack for secondary CPUs */ - REGION(stack_sec, BOOTROM_OFFSET + 0x180000, - CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000) - - /* Leave some space for the payload */ - POSTRAM_CBFS_CACHE(0x2000000, 16M) -} diff --git a/src/soc/cavium/cn81xx/memlayout.ld b/src/soc/cavium/cn81xx/memlayout.ld new file mode 100644 index 0000000000..79673c9974 --- /dev/null +++ b/src/soc/cavium/cn81xx/memlayout.ld @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +SECTIONS +{ + DRAM_START(0x00000000) + /* Secure region 0 - 1MiB */ + BL31(0, 0xe0000) + REGION(sff8104, 0xe0000, 0x20000, 0x1000) + + /* Insecure region 1MiB - TOP OF DRAM */ + /* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */ + SRAM_START(BOOTROM_OFFSET) + + STACK(BOOTROM_OFFSET, 16K) + TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) + PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) + FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) + PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) + BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) + VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) + TPM_TCPA_LOG(BOOTROM_OFFSET + 0x33000, 2K) + VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) + ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) + + SRAM_END(BOOTROM_OFFSET + 0x80000) + + TTB(BOOTROM_OFFSET + 0x80000, 512K) + RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) + /* Stack for secondary CPUs */ + REGION(stack_sec, BOOTROM_OFFSET + 0x180000, + CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000) + + /* Leave some space for the payload */ + POSTRAM_CBFS_CACHE(0x2000000, 16M) +} diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 6476d42b0a..15b833f56f 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -13,6 +13,10 @@ config SOC_MEDIATEK_MT8173 if SOC_MEDIATEK_MT8173 +config MEMLAYOUT_LD_FILE + string + default "src/soc/mediatek/mt8173/memlayout.ld" + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld deleted file mode 100644 index 4aece51cef..0000000000 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -/* - * SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM. - * It will be returned before starting the ramstage. - * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. - */ -#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) -#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) - -#define DRAM_DMA(addr, size) \ - REGION(dram_dma, addr, size, 4K) \ - _ = ASSERT(size % 4K == 0, \ - "DRAM DMA buffer should be multiple of smallest page size (4K)!"); - -SECTIONS -{ - SRAM_L2C_START(0x000C0000) - BOOTBLOCK(0x000C1000, 85K) - VERSTAGE(0x000D7000, 114K) - SRAM_L2C_END(0x00100000) - - SRAM_START(0x00100000) - VBOOT2_WORK(0x00100000, 12K) - TPM_TCPA_LOG(0x00103000, 2K) - FMAP_CACHE(0x00103800, 2K) - PRERAM_CBMEM_CONSOLE(0x00104000, 12K) - WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) - TIMESTAMP(0x0010B000, 4K) - ROMSTAGE(0x0010C000, 92K) - STACK(0x00124000, 16K) - TTB(0x00128000, 28K) - DMA_COHERENT(0x0012F000, 4K) - SRAM_END(0x00130000) - - DRAM_START(0x40000000) - DRAM_DMA(0x40000000, 1M) - POSTRAM_CBFS_CACHE(0x40100000, 1M) - RAMSTAGE(0x40200000, 256K) -} diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld new file mode 100644 index 0000000000..4aece51cef --- /dev/null +++ b/src/soc/mediatek/mt8173/memlayout.ld @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* + * SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) +#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) + +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + +SECTIONS +{ + SRAM_L2C_START(0x000C0000) + BOOTBLOCK(0x000C1000, 85K) + VERSTAGE(0x000D7000, 114K) + SRAM_L2C_END(0x00100000) + + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + TPM_TCPA_LOG(0x00103000, 2K) + FMAP_CACHE(0x00103800, 2K) + PRERAM_CBMEM_CONSOLE(0x00104000, 12K) + WATCHDOG_TOMBSTONE(0x00107000, 4) + PRERAM_CBFS_CACHE(0x00107004, 16K - 4) + TIMESTAMP(0x0010B000, 4K) + ROMSTAGE(0x0010C000, 92K) + STACK(0x00124000, 16K) + TTB(0x00128000, 28K) + DMA_COHERENT(0x0012F000, 4K) + SRAM_END(0x00130000) + + DRAM_START(0x40000000) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 1M) + RAMSTAGE(0x40200000, 256K) +} diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index 46249be038..82827d1755 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -11,6 +11,10 @@ config SOC_MEDIATEK_MT8183 if SOC_MEDIATEK_MT8183 +config MEMLAYOUT_LD_FILE + string + default "src/soc/mediatek/mt8183/memlayout.ld" + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld deleted file mode 100644 index a26637766b..0000000000 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -/* - * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. - * It will be returned before starting the ramstage. - * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. - */ -#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) -#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) -#define DRAM_INIT_CODE(addr, size) \ - REGION(dram_init_code, addr, size, 4) - -SECTIONS -{ - SRAM_START(0x00100000) - VBOOT2_WORK(0x00100000, 12K) - TPM_TCPA_LOG(0x00103000, 2K) - FMAP_CACHE(0x00103800, 2K) - WATCHDOG_TOMBSTONE(0x00104000, 4) - PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) - TIMESTAMP(0x00113c00, 1K) - STACK(0x00114000, 16K) - TTB(0x00118000, 28K) - DMA_COHERENT(0x0011f000, 4K) - SRAM_END(0x00120000) - - SRAM_L2C_START(0x00200000) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) - BOOTBLOCK(0x00230000, 64K) - DRAM_INIT_CODE(0x00240000, 208K) - PRERAM_CBFS_CACHE(0x00274000, 48K) - SRAM_L2C_END(0x00280000) - - DRAM_START(0x40000000) - POSTRAM_CBFS_CACHE(0x40000000, 2M) - RAMSTAGE(0x40200000, 256K) - - BL31(0x54600000, 0x60000) -} diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld new file mode 100644 index 0000000000..a26637766b --- /dev/null +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) +#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4) + +SECTIONS +{ + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + TPM_TCPA_LOG(0x00103000, 2K) + FMAP_CACHE(0x00103800, 2K) + WATCHDOG_TOMBSTONE(0x00104000, 4) + PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) + TIMESTAMP(0x00113c00, 1K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) + SRAM_END(0x00120000) + + SRAM_L2C_START(0x00200000) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) + BOOTBLOCK(0x00230000, 64K) + DRAM_INIT_CODE(0x00240000, 208K) + PRERAM_CBFS_CACHE(0x00274000, 48K) + SRAM_L2C_END(0x00280000) + + DRAM_START(0x40000000) + POSTRAM_CBFS_CACHE(0x40000000, 2M) + RAMSTAGE(0x40200000, 256K) + + BL31(0x54600000, 0x60000) +} diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index c962aead71..deca2cda96 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -15,6 +15,10 @@ config SOC_NVIDIA_TEGRA124 if SOC_NVIDIA_TEGRA124 +config MEMLAYOUT_LD_FILE + string + default "src/soc/nvidia/tegra124/memlayout.ld" + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld deleted file mode 100644 index 94b6fd8d91..0000000000 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -/* - * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, - * so the bootblock loading address must be placed after that. After the - * handoff that area may be reclaimed for other uses, e.g. CBFS cache. - */ - -SECTIONS -{ - SRAM_START(0x40000000) - TTB(0x40000000, 16K + 32) - PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) - FMAP_CACHE(0x40005800, 2K) - PRERAM_CBFS_CACHE(0x40006000, 14K) - VBOOT2_WORK(0x40009800, 12K) - TPM_TCPA_LOG(0x4000D800, 2K) - STACK(0x4000E000, 8K) - BOOTBLOCK(0x40010000, 30K) - VERSTAGE(0x40017800, 72K) - ROMSTAGE(0x40029800, 89K) - TIMESTAMP(0x4003FC00, 1K) - SRAM_END(0x40040000) - - DRAM_START(0x80000000) - POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 128K) - DMA_COHERENT(0x90000000, 2M) -} diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld new file mode 100644 index 0000000000..94b6fd8d91 --- /dev/null +++ b/src/soc/nvidia/tegra124/memlayout.ld @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* + * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, + * so the bootblock loading address must be placed after that. After the + * handoff that area may be reclaimed for other uses, e.g. CBFS cache. + */ + +SECTIONS +{ + SRAM_START(0x40000000) + TTB(0x40000000, 16K + 32) + PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) + FMAP_CACHE(0x40005800, 2K) + PRERAM_CBFS_CACHE(0x40006000, 14K) + VBOOT2_WORK(0x40009800, 12K) + TPM_TCPA_LOG(0x4000D800, 2K) + STACK(0x4000E000, 8K) + BOOTBLOCK(0x40010000, 30K) + VERSTAGE(0x40017800, 72K) + ROMSTAGE(0x40029800, 89K) + TIMESTAMP(0x4003FC00, 1K) + SRAM_END(0x40040000) + + DRAM_START(0x80000000) + POSTRAM_CBFS_CACHE(0x80100000, 1M) + RAMSTAGE(0x80200000, 128K) + DMA_COHERENT(0x90000000, 2M) +} diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 780fa18744..32748f3b6b 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -13,6 +13,10 @@ config SOC_NVIDIA_TEGRA210 if SOC_NVIDIA_TEGRA210 +config MEMLAYOUT_LD_FILE + string + default "src/soc/nvidia/tegra210/memlayout.ld" + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld deleted file mode 100644 index e5620bcf6a..0000000000 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#include - -/* - * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, - * so the bootblock loading address must be placed after that. After the - * handoff that area may be reclaimed for other uses, e.g. CBFS cache. - * TODO: Did this change on Tegra210? What's the new valid range? - */ - -SECTIONS -{ - SRAM_START(0x40000000) - PRERAM_CBMEM_CONSOLE(0x40000000, 2K) - FMAP_CACHE(0x40000800, 2K) - PRERAM_CBFS_CACHE(0x40001000, 28K) - VBOOT2_WORK(0x40008000, 12K) - TPM_TCPA_LOG(0x4000B000, 2K) -#if ENV_ARM64 - STACK(0x4000B800, 3K) -#else /* AVP gets a separate stack to avoid any chance of handoff races. */ - STACK(0x4000C400, 3K) -#endif - TIMESTAMP(0x4000D000, 2K) - BOOTBLOCK(0x4000D800, 42K) - OVERLAP_VERSTAGE_ROMSTAGE(0x40018000, 160K) - SRAM_END(0x40040000) - - DRAM_START(0x80000000) - POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 256K) - TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M) -} diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld new file mode 100644 index 0000000000..e5620bcf6a --- /dev/null +++ b/src/soc/nvidia/tegra210/memlayout.ld @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +/* + * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, + * so the bootblock loading address must be placed after that. After the + * handoff that area may be reclaimed for other uses, e.g. CBFS cache. + * TODO: Did this change on Tegra210? What's the new valid range? + */ + +SECTIONS +{ + SRAM_START(0x40000000) + PRERAM_CBMEM_CONSOLE(0x40000000, 2K) + FMAP_CACHE(0x40000800, 2K) + PRERAM_CBFS_CACHE(0x40001000, 28K) + VBOOT2_WORK(0x40008000, 12K) + TPM_TCPA_LOG(0x4000B000, 2K) +#if ENV_ARM64 + STACK(0x4000B800, 3K) +#else /* AVP gets a separate stack to avoid any chance of handoff races. */ + STACK(0x4000C400, 3K) +#endif + TIMESTAMP(0x4000D000, 2K) + BOOTBLOCK(0x4000D800, 42K) + OVERLAP_VERSTAGE_ROMSTAGE(0x40018000, 160K) + SRAM_END(0x40040000) + + DRAM_START(0x80000000) + POSTRAM_CBFS_CACHE(0x80100000, 1M) + RAMSTAGE(0x80200000, 256K) + TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M) +} diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index ef80772b2f..0eabb00752 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -10,6 +10,10 @@ config SOC_QC_IPQ40XX if SOC_QC_IPQ40XX +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/ipq40xx/memlayout.ld" + config GENERIC_UDELAY def_bool n diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld deleted file mode 100644 index 1a2dd31cc4..0000000000 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -#define REGION_START(name, addr) SYMBOL(name, addr) -#define REGION_END(name, addr) SYMBOL(e##name, addr) - -SECTIONS -{ - REGION(oc_imem, 0x08600000, 32K, 0) - - /* ==vvv== OC_IMEM_1_START 0x08600000 ==vvv== */ -/* DDR(0x08600000, 32K) */ - /* ==^^^== OC_IMEM_1_END 0x08608000 ==^^^== */ - - /* ==vvv== WIFI_IMEM_0_START 0x0A0C0000 ==vvv== */ - REGION_START(wifi_imem_0, 0x0A0C0000) - /* This includes bootblock image, can be reused after bootblock starts */ -/* UBER_SBL(0x0A0C0000, 48K) */ - - PRERAM_CBFS_CACHE(0x0A0C0000, 92K) - FMAP_CACHE(0x0A0EF800, 2K) - - TTB(0x0A0F0000, 16K) - TTB_SUBTABLES(0x0A0F4000, 4K) - REGION_END(wifi_imem_0, 0x0A100000) - /* ==^^^== WIFI_IMEM_0_END 0x0A100000 ==^^^== */ - - - /* ==vvv== WIFI_IMEM_1_START 0x0A8C0000 ==vvv== */ - REGION_START(wifi_imem_1, 0x0A8C0000) - BOOTBLOCK(0x0A8C0000, 24K) - OVERLAP_VERSTAGE_ROMSTAGE(0x0A8C6000, 64K) - VBOOT2_WORK(0x0A8D6000, 12K) - PRERAM_CBMEM_CONSOLE(0x0A8DA000, 32K) - TIMESTAMP(0x0A8E2000, 1K) - -/* 0x0A8E2400..0x0A8FC000 103 KB free */ - - STACK(0x0A8FC000, 16K) - REGION_END(wifi_imem_1, 0x0A900000) - /* ==^^^== WIFI_IMEM_1_END 0x0A900000 ==^^^== */ - - DRAM_START(0x80000000) - SYMBOL(memlayout_cbmem_top, 0x87280000) - POSTRAM_CBFS_CACHE(0x87280000, 512K) - RAMSTAGE(0x87300000, 512K) - DMA_COHERENT(0x87400000, 2M) -} diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld new file mode 100644 index 0000000000..1a2dd31cc4 --- /dev/null +++ b/src/soc/qualcomm/ipq40xx/memlayout.ld @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +#define REGION_START(name, addr) SYMBOL(name, addr) +#define REGION_END(name, addr) SYMBOL(e##name, addr) + +SECTIONS +{ + REGION(oc_imem, 0x08600000, 32K, 0) + + /* ==vvv== OC_IMEM_1_START 0x08600000 ==vvv== */ +/* DDR(0x08600000, 32K) */ + /* ==^^^== OC_IMEM_1_END 0x08608000 ==^^^== */ + + /* ==vvv== WIFI_IMEM_0_START 0x0A0C0000 ==vvv== */ + REGION_START(wifi_imem_0, 0x0A0C0000) + /* This includes bootblock image, can be reused after bootblock starts */ +/* UBER_SBL(0x0A0C0000, 48K) */ + + PRERAM_CBFS_CACHE(0x0A0C0000, 92K) + FMAP_CACHE(0x0A0EF800, 2K) + + TTB(0x0A0F0000, 16K) + TTB_SUBTABLES(0x0A0F4000, 4K) + REGION_END(wifi_imem_0, 0x0A100000) + /* ==^^^== WIFI_IMEM_0_END 0x0A100000 ==^^^== */ + + + /* ==vvv== WIFI_IMEM_1_START 0x0A8C0000 ==vvv== */ + REGION_START(wifi_imem_1, 0x0A8C0000) + BOOTBLOCK(0x0A8C0000, 24K) + OVERLAP_VERSTAGE_ROMSTAGE(0x0A8C6000, 64K) + VBOOT2_WORK(0x0A8D6000, 12K) + PRERAM_CBMEM_CONSOLE(0x0A8DA000, 32K) + TIMESTAMP(0x0A8E2000, 1K) + +/* 0x0A8E2400..0x0A8FC000 103 KB free */ + + STACK(0x0A8FC000, 16K) + REGION_END(wifi_imem_1, 0x0A900000) + /* ==^^^== WIFI_IMEM_1_END 0x0A900000 ==^^^== */ + + DRAM_START(0x80000000) + SYMBOL(memlayout_cbmem_top, 0x87280000) + POSTRAM_CBFS_CACHE(0x87280000, 512K) + RAMSTAGE(0x87300000, 512K) + DMA_COHERENT(0x87400000, 2M) +} diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index fa0fefef67..7de2a99f1e 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -11,6 +11,10 @@ config SOC_QC_IPQ806X if SOC_QC_IPQ806X +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/ipq806x/memlayout.ld" + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_FLASH diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld deleted file mode 100644 index 6e7e56cada..0000000000 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -SECTIONS -{ - REGION(rpm, 0x00020000, 160K, 8K) - SRAM_START(0x2A000000) - /* This includes bootblock image, can be reused after bootblock starts */ -/* UBER_SBL(0x2A000000, 48K) */ -/* DDR(0x2A000000, 48K) */ - BOOTBLOCK(0x2A00C000, 24K) - OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K) - VBOOT2_WORK(0x2A022000, 12K) - PRERAM_CBMEM_CONSOLE(0x2A026000, 32K) - TIMESTAMP(0x2A02E000, 1K) - -/* 0x2e400..0x3F000 67 KB free */ - -/* Keep the below area reserved at all times, it is used by various QCA - components as shared data - QCA_SHARED_RAM(2A03F000, 4K) -*/ - STACK(0x2A040000, 16K) - PRERAM_CBFS_CACHE(0x2A044000, 91K) - FMAP_CACHE(0x2A05B000, 2K) - TTB_SUBTABLES(0x2A05B800, 2K) - TTB(0x2A05C000, 16K) - SRAM_END(0x2A060000) - - DRAM_START(0x40000000) - RAMSTAGE(0x40640000, 128K) - SYMBOL(memlayout_cbmem_top, 0x59F80000) - POSTRAM_CBFS_CACHE(0x59F80000, 384K) - DMA_COHERENT(0x5A000000, 2M) -} diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld new file mode 100644 index 0000000000..6e7e56cada --- /dev/null +++ b/src/soc/qualcomm/ipq806x/memlayout.ld @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +SECTIONS +{ + REGION(rpm, 0x00020000, 160K, 8K) + SRAM_START(0x2A000000) + /* This includes bootblock image, can be reused after bootblock starts */ +/* UBER_SBL(0x2A000000, 48K) */ +/* DDR(0x2A000000, 48K) */ + BOOTBLOCK(0x2A00C000, 24K) + OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K) + VBOOT2_WORK(0x2A022000, 12K) + PRERAM_CBMEM_CONSOLE(0x2A026000, 32K) + TIMESTAMP(0x2A02E000, 1K) + +/* 0x2e400..0x3F000 67 KB free */ + +/* Keep the below area reserved at all times, it is used by various QCA + components as shared data + QCA_SHARED_RAM(2A03F000, 4K) +*/ + STACK(0x2A040000, 16K) + PRERAM_CBFS_CACHE(0x2A044000, 91K) + FMAP_CACHE(0x2A05B000, 2K) + TTB_SUBTABLES(0x2A05B800, 2K) + TTB(0x2A05C000, 16K) + SRAM_END(0x2A060000) + + DRAM_START(0x40000000) + RAMSTAGE(0x40640000, 128K) + SYMBOL(memlayout_cbmem_top, 0x59F80000) + POSTRAM_CBFS_CACHE(0x59F80000, 384K) + DMA_COHERENT(0x5A000000, 2M) +} diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 60d8e3af60..0dc96ba06a 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -13,6 +13,10 @@ config SOC_QUALCOMM_QCS405 if SOC_QUALCOMM_QCS405 +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/qcs405/memlayout.ld" + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld deleted file mode 100644 index ff2ad2f99c..0000000000 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */ -#define SSRAM_START(addr) SYMBOL(ssram, addr) -#define SSRAM_END(addr) SYMBOL(essram, addr) - -/* BOOT_IMEM : 0x8C00000 - 0x8D80000 */ -#define BSRAM_START(addr) SYMBOL(bsram, addr) -#define BSRAM_END(addr) SYMBOL(ebsram, addr) - -SECTIONS -{ - SSRAM_START(0x8600000) - SSRAM_END(0x8608000) - - BSRAM_START(0x8C00000) - OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K) - REGION(fw_reserved2, 0x8C19000, 0x16000, 4096) - BOOTBLOCK(0x8C2F000, 40K) - TTB(0x8C39000, 56K) - VBOOT2_WORK(0x8C47000, 12K) - STACK(0x8C4B000, 16K) - TIMESTAMP(0x8C4F000, 1K) - PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) - PRERAM_CBFS_CACHE(0x8C57400, 70K) - FMAP_CACHE(0x8C68C00, 2K) - REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100) - BSRAM_END(0x8D80000) - - DRAM_START(0x80000000) - /* DDR Carveout for BL31 usage */ - REGION(dram_reserved, 0x85000000, 0x5100000, 4096) - POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) -} diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld new file mode 100644 index 0000000000..ff2ad2f99c --- /dev/null +++ b/src/soc/qualcomm/qcs405/memlayout.ld @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x8C00000 - 0x8D80000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +SECTIONS +{ + SSRAM_START(0x8600000) + SSRAM_END(0x8608000) + + BSRAM_START(0x8C00000) + OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K) + REGION(fw_reserved2, 0x8C19000, 0x16000, 4096) + BOOTBLOCK(0x8C2F000, 40K) + TTB(0x8C39000, 56K) + VBOOT2_WORK(0x8C47000, 12K) + STACK(0x8C4B000, 16K) + TIMESTAMP(0x8C4F000, 1K) + PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) + PRERAM_CBFS_CACHE(0x8C57400, 70K) + FMAP_CACHE(0x8C68C00, 2K) + REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100) + BSRAM_END(0x8D80000) + + DRAM_START(0x80000000) + /* DDR Carveout for BL31 usage */ + REGION(dram_reserved, 0x85000000, 0x5100000, 4096) + POSTRAM_CBFS_CACHE(0x9F800000, 384K) + RAMSTAGE(0x9F860000, 128K) +} diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index faf036e62b..d3dab7acd9 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -16,6 +16,10 @@ config SOC_QUALCOMM_SC7180 if SOC_QUALCOMM_SC7180 +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/sc7180/memlayout.ld" + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld deleted file mode 100644 index 2a0cd8a417..0000000000 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */ -#define SSRAM_START(addr) SYMBOL(ssram, addr) -#define SSRAM_END(addr) SYMBOL(essram, addr) - -/* BOOT_IMEM : 0x14800000 - 0x14980000 */ -#define BSRAM_START(addr) SYMBOL(bsram, addr) -#define BSRAM_END(addr) SYMBOL(ebsram, addr) - -/* AOP : 0x0B000000 - 0x0B100000 */ -#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) -#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) - -SECTIONS -{ - AOPSRAM_START(0x0B000000) - REGION(aop, 0x0B000000, 0x100000, 4096) - AOPSRAM_END(0x0B100000) - - SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - REGION(qcsdi, 0x14699000, 52K, 4K) - SSRAM_END(0x146AE000) - - BSRAM_START(0x14800000) - REGION(pbl_timestamps, 0x14800000, 84K, 4K) - BOOTBLOCK(0x14815000, 40K) - PRERAM_CBFS_CACHE(0x1481F000, 70K) - PRERAM_CBMEM_CONSOLE(0x14830800, 32K) - TIMESTAMP(0x14838800, 1K) - TTB(0x14839000, 56K) - STACK(0x14847000, 16K) - VBOOT2_WORK(0x1484B000, 12K) - DMA_COHERENT(0x1484E000, 8K) - REGION(ddr_training, 0x14850000, 8K, 4K) - REGION(qclib_serial_log, 0x14852000, 4K, 4K) - REGION(ddr_information, 0x14853000, 1K, 1K) - FMAP_CACHE(0x14853400, 2K) - REGION(dcb, 0x14870000, 16K, 4K) - REGION(pmic, 0x14874000, 44K, 4K) - REGION(limits_cfg, 0x1487F000, 4K, 4K) - REGION(qclib, 0x14880000, 512K, 4K) - BSRAM_END(0x14900000) - - DRAM_START(0x80000000) - /* Various hardware/software subsystems make use of this area */ - REGION(dram_aop, 0x80800000, 0x040000, 0x1000) - REGION(dram_soc, 0x80900000, 0x200000, 0x1000) - BL31(0x80B00000, 1M) - POSTRAM_CBFS_CACHE(0x9F800000, 16M) - RAMSTAGE(0xA0800000, 16M) -} diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld new file mode 100644 index 0000000000..2a0cd8a417 --- /dev/null +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + +SECTIONS +{ + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146AE000) + + BSRAM_START(0x14800000) + REGION(pbl_timestamps, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14815000, 40K) + PRERAM_CBFS_CACHE(0x1481F000, 70K) + PRERAM_CBMEM_CONSOLE(0x14830800, 32K) + TIMESTAMP(0x14838800, 1K) + TTB(0x14839000, 56K) + STACK(0x14847000, 16K) + VBOOT2_WORK(0x1484B000, 12K) + DMA_COHERENT(0x1484E000, 8K) + REGION(ddr_training, 0x14850000, 8K, 4K) + REGION(qclib_serial_log, 0x14852000, 4K, 4K) + REGION(ddr_information, 0x14853000, 1K, 1K) + FMAP_CACHE(0x14853400, 2K) + REGION(dcb, 0x14870000, 16K, 4K) + REGION(pmic, 0x14874000, 44K, 4K) + REGION(limits_cfg, 0x1487F000, 4K, 4K) + REGION(qclib, 0x14880000, 512K, 4K) + BSRAM_END(0x14900000) + + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_aop, 0x80800000, 0x040000, 0x1000) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 1M) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) +} diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index dbe025e93a..c93ec6c1bb 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -12,6 +12,10 @@ config SOC_QUALCOMM_SDM845 if SOC_QUALCOMM_SDM845 +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/sdm845/memlayout.ld" + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld deleted file mode 100644 index 30b4920288..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -/* SYSTEM_IMEM : 0x14680000 - 0x146C0000 */ -#define SSRAM_START(addr) SYMBOL(ssram, addr) -#define SSRAM_END(addr) SYMBOL(essram, addr) - -/* BOOT_IMEM : 0x14800000 - 0x14980000 */ -#define BSRAM_START(addr) SYMBOL(bsram, addr) -#define BSRAM_END(addr) SYMBOL(ebsram, addr) - -/* AOP : 0x0B000000 - 0x0B100000 */ -#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) -#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) - -/* AOPMSG : 0x0C300000 - 0x0C400000 */ -#define AOPMSG_START(addr) SYMBOL(aopmsg, addr) -#define AOPMSG_END(addr) SYMBOL(eaopmsg, addr) - -SECTIONS -{ - AOPSRAM_START(0x0B000000) - REGION(aop, 0x0B000000, 0x100000, 4096) - AOPSRAM_END(0x0B100000) - - AOPMSG_START(0x0C300000) - REGION(aop_ss_msg_ram_drv15, 0x0C3F0000, 0x400, 0x100) - AOPMSG_END(0x0C400000) - - SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - DMA_COHERENT(0x14699000, 8K) - REGION(qcsdi, 0x146AC000, 44K, 4K) - SSRAM_END(0x146C0000) - - BSRAM_START(0x14800000) - REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000) - BOOTBLOCK(0x14816000, 40K) - TTB(0x14820000, 56K) - VBOOT2_WORK(0x1482E000, 12K) - STACK(0x14832000, 16K) - TIMESTAMP(0x14836000, 1K) - PRERAM_CBMEM_CONSOLE(0x14836400, 32K) - PRERAM_CBFS_CACHE(0x1483E400, 70K) - FMAP_CACHE(0x1484FC00, 2K) - REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) - REGION(ddr_information, 0x148EDF00, 256, 256) - REGION(limits_cfg, 0x148EE000, 4K, 4K) - REGION(qclib_serial_log, 0x148EF000, 4K, 4K) - REGION(ddr_training, 0x148F0000, 8K, 4K) - REGION(qclib, 0x148F2000, 512K, 4K) - REGION(dcb, 0x14972000, 16K, 4K) - REGION(pmic, 0x14976000, 40K, 4K) - BSRAM_END(0x14980000) - - DRAM_START(0x80000000) - /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 0x1000) - POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 2M) -} diff --git a/src/soc/qualcomm/sdm845/memlayout.ld b/src/soc/qualcomm/sdm845/memlayout.ld new file mode 100644 index 0000000000..30b4920288 --- /dev/null +++ b/src/soc/qualcomm/sdm845/memlayout.ld @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* SYSTEM_IMEM : 0x14680000 - 0x146C0000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + +/* AOPMSG : 0x0C300000 - 0x0C400000 */ +#define AOPMSG_START(addr) SYMBOL(aopmsg, addr) +#define AOPMSG_END(addr) SYMBOL(eaopmsg, addr) + +SECTIONS +{ + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + AOPMSG_START(0x0C300000) + REGION(aop_ss_msg_ram_drv15, 0x0C3F0000, 0x400, 0x100) + AOPMSG_END(0x0C400000) + + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + DMA_COHERENT(0x14699000, 8K) + REGION(qcsdi, 0x146AC000, 44K, 4K) + SSRAM_END(0x146C0000) + + BSRAM_START(0x14800000) + REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000) + BOOTBLOCK(0x14816000, 40K) + TTB(0x14820000, 56K) + VBOOT2_WORK(0x1482E000, 12K) + STACK(0x14832000, 16K) + TIMESTAMP(0x14836000, 1K) + PRERAM_CBMEM_CONSOLE(0x14836400, 32K) + PRERAM_CBFS_CACHE(0x1483E400, 70K) + FMAP_CACHE(0x1484FC00, 2K) + REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) + REGION(ddr_information, 0x148EDF00, 256, 256) + REGION(limits_cfg, 0x148EE000, 4K, 4K) + REGION(qclib_serial_log, 0x148EF000, 4K, 4K) + REGION(ddr_training, 0x148F0000, 8K, 4K) + REGION(qclib, 0x148F2000, 512K, 4K) + REGION(dcb, 0x14972000, 16K, 4K) + REGION(pmic, 0x14976000, 40K, 4K) + BSRAM_END(0x14980000) + + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_reserved, 0x85000000, 0x1A800000, 0x1000) + POSTRAM_CBFS_CACHE(0x9F800000, 384K) + RAMSTAGE(0x9F860000, 2M) +} diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3198aa4324..3dc9a9b554 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -20,6 +20,10 @@ config SOC_ROCKCHIP_RK3288 if SOC_ROCKCHIP_RK3288 +config MEMLAYOUT_LD_FILE + string + default "src/soc/rockchip/rk3288/memlayout.ld" + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld deleted file mode 100644 index 4ef0163def..0000000000 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -/* Note: The BootROM will jump to 0xFF704004 after loading bootblock, - * so the bootblock loading address must be at 0xFF704004. - */ -SECTIONS -{ - DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) - POSTRAM_CBFS_CACHE(0x01000000, 1M) - DMA_COHERENT(0x10000000, 2M) - FRAMEBUFFER(0x10800000, 8M) - - SRAM_START(0xFF700000) - TTB(0xFF700000, 16K) - BOOTBLOCK(0xFF704004, 16K - 4) - PRERAM_CBMEM_CONSOLE(0xFF708000, 2K) - VBOOT2_WORK(0xFF708800, 12K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768) - PRERAM_CBFS_CACHE(0xFF717300, 256) - TIMESTAMP(0xFF717400, 0x180) - STACK(0xFF717580, 3K - 0x180) - SRAM_END(0xFF718000) - - /* 4K of special SRAM in PMU power domain. - * Careful: only supports 32-bit wide write accesses! */ - SYMBOL(pmu_sram, 0xFF720000) - TTB_SUBTABLES(0xFF720800, 1K) - WATCHDOG_TOMBSTONE(0xFF720FFC, 4) - SYMBOL(epmu_sram, 0xFF721000) -} diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld new file mode 100644 index 0000000000..4ef0163def --- /dev/null +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* Note: The BootROM will jump to 0xFF704004 after loading bootblock, + * so the bootblock loading address must be at 0xFF704004. + */ +SECTIONS +{ + DRAM_START(0x00000000) + RAMSTAGE(0x00200000, 128K) + POSTRAM_CBFS_CACHE(0x01000000, 1M) + DMA_COHERENT(0x10000000, 2M) + FRAMEBUFFER(0x10800000, 8M) + + SRAM_START(0xFF700000) + TTB(0xFF700000, 16K) + BOOTBLOCK(0xFF704004, 16K - 4) + PRERAM_CBMEM_CONSOLE(0xFF708000, 2K) + VBOOT2_WORK(0xFF708800, 12K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768) + PRERAM_CBFS_CACHE(0xFF717300, 256) + TIMESTAMP(0xFF717400, 0x180) + STACK(0xFF717580, 3K - 0x180) + SRAM_END(0xFF718000) + + /* 4K of special SRAM in PMU power domain. + * Careful: only supports 32-bit wide write accesses! */ + SYMBOL(pmu_sram, 0xFF720000) + TTB_SUBTABLES(0xFF720800, 1K) + WATCHDOG_TOMBSTONE(0xFF720FFC, 4) + SYMBOL(epmu_sram, 0xFF721000) +} diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 7e3c44b674..4f7af9e0c2 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -14,6 +14,10 @@ config SOC_ROCKCHIP_RK3399 if SOC_ROCKCHIP_RK3399 +config MEMLAYOUT_LD_FILE + string + default "src/soc/rockchip/rk3399/memlayout.ld" + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld deleted file mode 100644 index 72836b5130..0000000000 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -SECTIONS -{ - DRAM_START(0x00000000) - BL31(0, 0x100000) - POSTRAM_CBFS_CACHE(0x00100000, 8M) - RAMSTAGE(0x00900000, 2M) - DMA_COHERENT(0x10000000, 2M) - - /* 8K of special SRAM in PMU power domain. */ - SYMBOL(pmu_sram, 0xFF3B0000) - WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4) - SYMBOL(epmu_sram, 0xFF3B2000) - - SRAM_START(0xFF8C0000) -#if ENV_RAMSTAGE - REGION(bl31_sram, 0xFF8C0000, 64K, 1) -#else - PRERAM_CBFS_CACHE(0xFF8C0000, 5K) - FMAP_CACHE(0xFF8C1400, 2K) - TIMESTAMP(0xFF8C1C00, 1K) - /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) - BOOTBLOCK(0xFF8D8000, 40K) -#endif - VBOOT2_WORK(0XFF8E2000, 12K) - TTB(0xFF8E5000, 24K) - PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) - STACK(0xFF8ED000, 12K) - SRAM_END(0xFF8F0000) -} diff --git a/src/soc/rockchip/rk3399/memlayout.ld b/src/soc/rockchip/rk3399/memlayout.ld new file mode 100644 index 0000000000..72836b5130 --- /dev/null +++ b/src/soc/rockchip/rk3399/memlayout.ld @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +SECTIONS +{ + DRAM_START(0x00000000) + BL31(0, 0x100000) + POSTRAM_CBFS_CACHE(0x00100000, 8M) + RAMSTAGE(0x00900000, 2M) + DMA_COHERENT(0x10000000, 2M) + + /* 8K of special SRAM in PMU power domain. */ + SYMBOL(pmu_sram, 0xFF3B0000) + WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4) + SYMBOL(epmu_sram, 0xFF3B2000) + + SRAM_START(0xFF8C0000) +#if ENV_RAMSTAGE + REGION(bl31_sram, 0xFF8C0000, 64K, 1) +#else + PRERAM_CBFS_CACHE(0xFF8C0000, 5K) + FMAP_CACHE(0xFF8C1400, 2K) + TIMESTAMP(0xFF8C1C00, 1K) + /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) + BOOTBLOCK(0xFF8D8000, 40K) +#endif + VBOOT2_WORK(0XFF8E2000, 12K) + TTB(0xFF8E5000, 24K) + PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) + STACK(0xFF8ED000, 12K) + SRAM_END(0xFF8F0000) +} diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 680bd66cb7..28a89fa9c8 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -9,6 +9,10 @@ config CPU_SAMSUNG_EXYNOS5250 if CPU_SAMSUNG_EXYNOS5250 +config MEMLAYOUT_LD_FILE + string + default "src/soc/samsung/exynos5250/memlayout.ld" + config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld deleted file mode 100644 index be4bb6edd7..0000000000 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -/* - * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock - * must be placed after that. After the handoff, the space can be reclaimed. - */ - -SECTIONS -{ - SRAM_START(0x2020000) - /* 13K hole, includes BL1 */ - BOOTBLOCK(0x2023400, 32K) - /* 19K hole */ - ROMSTAGE(0x2030000, 128K) - /* 32K hole */ - TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 76K) - FMAP_CACHE(0x206F000, 2K) - TPM_TCPA_LOG(0x206F800, 2K) - VBOOT2_WORK(0x2070000, 12K) - STACK(0x2074000, 16K) - SRAM_END(0x2078000) - - DRAM_START(0x40000000) - RAMSTAGE(0x40000000, 128K) - POSTRAM_CBFS_CACHE(0x41000000, 8M) - DMA_COHERENT(0x77300000, 1M) -} diff --git a/src/soc/samsung/exynos5250/memlayout.ld b/src/soc/samsung/exynos5250/memlayout.ld new file mode 100644 index 0000000000..be4bb6edd7 --- /dev/null +++ b/src/soc/samsung/exynos5250/memlayout.ld @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* + * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock + * must be placed after that. After the handoff, the space can be reclaimed. + */ + +SECTIONS +{ + SRAM_START(0x2020000) + /* 13K hole, includes BL1 */ + BOOTBLOCK(0x2023400, 32K) + /* 19K hole */ + ROMSTAGE(0x2030000, 128K) + /* 32K hole */ + TTB(0x2058000, 16K) + PRERAM_CBFS_CACHE(0x205C000, 76K) + FMAP_CACHE(0x206F000, 2K) + TPM_TCPA_LOG(0x206F800, 2K) + VBOOT2_WORK(0x2070000, 12K) + STACK(0x2074000, 16K) + SRAM_END(0x2078000) + + DRAM_START(0x40000000) + RAMSTAGE(0x40000000, 128K) + POSTRAM_CBFS_CACHE(0x41000000, 8M) + DMA_COHERENT(0x77300000, 1M) +} diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 3af8e64ac3..1b80ffca32 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -11,6 +11,10 @@ config CPU_SAMSUNG_EXYNOS5420 if CPU_SAMSUNG_EXYNOS5420 +config MEMLAYOUT_LD_FILE + string + default "src/soc/samsung/exynos5420/memlayout.ld" + config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld deleted file mode 100644 index e29900110e..0000000000 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -/* - * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock - * must be placed after that. After the handoff, the space can be reclaimed. - */ - -SECTIONS -{ - SRAM_START(0x2020000) - /* 17K hole, includes BL1 */ - /* Bootblock is preceded by 16 byte variable length BL2 checksum. */ - BOOTBLOCK(0x2024410, 32K - 16) - /* 15K hole */ - ROMSTAGE(0x2030000, 128K) - /* 32K hole */ - TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 74K) - FMAP_CACHE(0x206E800, 2K) - STACK(0x206F000, 16K) - /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't - * seem to be implemented right now? */ - SRAM_END(0x2074000) - - DRAM_START(0x20000000) - RAMSTAGE(0x20000000, 128K) - POSTRAM_CBFS_CACHE(0x21000000, 8M) - DMA_COHERENT(0x77300000, 1M) -} diff --git a/src/soc/samsung/exynos5420/memlayout.ld b/src/soc/samsung/exynos5420/memlayout.ld new file mode 100644 index 0000000000..e29900110e --- /dev/null +++ b/src/soc/samsung/exynos5420/memlayout.ld @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* + * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock + * must be placed after that. After the handoff, the space can be reclaimed. + */ + +SECTIONS +{ + SRAM_START(0x2020000) + /* 17K hole, includes BL1 */ + /* Bootblock is preceded by 16 byte variable length BL2 checksum. */ + BOOTBLOCK(0x2024410, 32K - 16) + /* 15K hole */ + ROMSTAGE(0x2030000, 128K) + /* 32K hole */ + TTB(0x2058000, 16K) + PRERAM_CBFS_CACHE(0x205C000, 74K) + FMAP_CACHE(0x206E800, 2K) + STACK(0x206F000, 16K) + /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't + * seem to be implemented right now? */ + SRAM_END(0x2074000) + + DRAM_START(0x20000000) + RAMSTAGE(0x20000000, 128K) + POSTRAM_CBFS_CACHE(0x21000000, 8M) + DMA_COHERENT(0x77300000, 1M) +} diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 64985bd0f0..4aa496131c 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -17,6 +17,10 @@ config SOC_SIFIVE_FU540 if SOC_SIFIVE_FU540 +config MEMLAYOUT_LD_FILE + string + default "src/soc/sifive/fu540/memlayout.ld" + config RISCV_ARCH string default "rv64imac" diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld deleted file mode 100644 index fd63dc0b45..0000000000 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#include - -#define L2LIM_START(addr) SYMBOL(l2lim, addr) -#define L2LIM_END(addr) SYMBOL(el2lim, addr) - -SECTIONS -{ - L2LIM_START(FU540_L2LIM) - BOOTBLOCK(FU540_L2LIM, 64K) - CAR_STACK(FU540_L2LIM + 64K, 20K) - PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) - FMAP_CACHE(FU540_L2LIM + 92K, 2K) - ROMSTAGE(FU540_L2LIM + 128K, 128K) - PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) - L2LIM_END(FU540_L2LIM + 2M) - - DRAM_START(FU540_DRAM) - REGION(opensbi, FU540_DRAM, 128K, 4K) - RAMSTAGE(FU540_DRAM + 128K, 256K) - MEM_STACK(FU540_DRAM + 448K, 20K) - POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) -} diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld new file mode 100644 index 0000000000..fd63dc0b45 --- /dev/null +++ b/src/soc/sifive/fu540/memlayout.ld @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +#define L2LIM_START(addr) SYMBOL(l2lim, addr) +#define L2LIM_END(addr) SYMBOL(el2lim, addr) + +SECTIONS +{ + L2LIM_START(FU540_L2LIM) + BOOTBLOCK(FU540_L2LIM, 64K) + CAR_STACK(FU540_L2LIM + 64K, 20K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + FMAP_CACHE(FU540_L2LIM + 92K, 2K) + ROMSTAGE(FU540_L2LIM + 128K, 128K) + PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) + L2LIM_END(FU540_L2LIM + 2M) + + DRAM_START(FU540_DRAM) + REGION(opensbi, FU540_DRAM, 128K, 4K) + RAMSTAGE(FU540_DRAM + 128K, 256K) + MEM_STACK(FU540_DRAM + 448K, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) +} -- cgit v1.2.3