From 45e16fc19913224c124cba0ca0ac22e949de9e9a Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 10 Oct 2014 01:31:02 -0700 Subject: t132: Enable SMMU translations BUG=None BRANCH=None TEST=Verified by reading back the value of SMMU_CONFIG register that enable bit is set to 1 Original-Change-Id: Iccc870141f9b9729971bf12119f9f3dae8181a43 Original-Signed-off-by: Furquan Shaikh Original-Reviewed-on: https://chromium-review.googlesource.com/222770 Original-Reviewed-by: Olof Johansson Original-Reviewed-by: Aaron Durbin Original-Tested-by: Furquan Shaikh Original-Commit-Queue: Furquan Shaikh (cherry picked from commit a06b36f9003d801709d83a8faed6fc04bb91df1b) Signed-off-by: Aaron Durbin Change-Id: Iae3949940a5a0efa2761542974d5c209178ce397 Reviewed-on: http://review.coreboot.org/9258 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra132/addressmap.c | 3 +++ src/soc/nvidia/tegra132/mc.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index 3df15b7841..a18e1b86dc 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -188,4 +188,7 @@ void trustzone_region_init(void) /* Set the carveout region. */ write32(tz_base_mib << 20, &mc->security_cfg0); write32(tz_size_mib, &mc->security_cfg1); + + /* Enable SMMU translations */ + write32(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config); } diff --git a/src/soc/nvidia/tegra132/mc.h b/src/soc/nvidia/tegra132/mc.h index c9faa498ac..3ce790022b 100644 --- a/src/soc/nvidia/tegra132/mc.h +++ b/src/soc/nvidia/tegra132/mc.h @@ -117,6 +117,8 @@ struct tegra_mc_regs { }; enum { + MC_SMMU_CONFIG_ENABLE = 1, + MC_EMEM_CFG_SIZE_MB_SHIFT = 0, MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff, -- cgit v1.2.3