From 436eac827aea4839169f2421006df42b8c5c379f Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Fri, 12 Nov 2021 11:28:15 +0100 Subject: mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree With latest hardware revision all clock outputs will be used on this mainboard. For this reason set all clock source mappings to 'PCIE_CLK_FREE' to have a free running clock. Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 39789be85a..ca905576b0 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -55,9 +55,9 @@ chip soc/intel/elkhartlake register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" -- cgit v1.2.3