From 42e4dd5aef69b3bb4962368317acac3e050a9e99 Mon Sep 17 00:00:00 2001 From: Raymond Chung Date: Tue, 30 Jul 2024 12:03:28 +0800 Subject: mb/google/brya/var/xol: Using baseboard's PchPmSlpAMinAssert settings Reduce PchPmSlpAMinAssert (pch_slp_a_min_assertion_width) to minimum time (98ms) from 2sec. BUG=b:349595391 BRANCH=firmware-brya-14505.B Test=Verified on xol Change-Id: Ia4b7b7ab5dc9afeb3505dfd2b42d0d397aed7a5c Signed-off-by: Raymond Chung Reviewed-on: https://review.coreboot.org/c/coreboot/+/83683 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/xol/overridetree.cb | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index 5de8c73260..529cb37a89 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -23,8 +23,6 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" - register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_DEFAULT" - # As per Intel Advisory doc#723158, the change is required to prevent possible # display flickering issue. register "disable_dynamic_tccold_handshake" = "true" -- cgit v1.2.3