From 3fd5a1bbbb7a112544975045a0c4ac1f3ea82202 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Tue, 19 May 2020 20:21:36 +0530 Subject: mb/google/dedede: Enable coreboot lock down config TEST=Build and boot waddledoo board Change-Id: Ic10af9a0d50946a98a5c4a77b492d242cef171ca Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/41535 Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index fc4397689e..72ce7c1821 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -140,6 +140,7 @@ chip soc/intel/jasperlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -151,6 +152,7 @@ chip soc/intel/jasperlake #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = 1, -- cgit v1.2.3