From 3d6d1075b2ba17a357143f518715a911e09b38ec Mon Sep 17 00:00:00 2001
From: Tim Chu <Tim.Chu@quantatw.com>
Date: Mon, 14 Dec 2020 23:30:13 -0800
Subject: soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed

Override SMBIOS type 4 max speed. This field should be maximum speed
supported by the system. 3900MHz is expected for Cooper Lake.

Tested=Execute "dmidecode -t 4" to check max speed is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/xeon_sp/cpx/ramstage.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c
index deb9030c20..1e0ba008c2 100644
--- a/src/soc/intel/xeon_sp/cpx/ramstage.c
+++ b/src/soc/intel/xeon_sp/cpx/ramstage.c
@@ -1,8 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <fsp/api.h>
+#include <smbios.h>
 
 int soc_fsp_multi_phase_init_is_enable(void)
 {
 	return 0;
 }
+
+unsigned int smbios_cpu_get_max_speed_mhz(void)
+{
+	return 3900;
+}
-- 
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