From 3b1a42f95d3f259f18b5f211dd112d03df9f78dd Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Tue, 25 Dec 2018 12:00:39 +0530 Subject: mb/google/hatch: Enable LPC/eSPI controller Enable LPC/eSPI controller(D31:F0). EC would be using eSPI interface, since the strap GPP_C5 is pulled up. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/30423 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Rizwan Qureshi --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 3cdc3e01a1..164c842485 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -96,7 +96,7 @@ chip soc/intel/cannonlake end end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 off end # LPC/eSPI + device pci 1f.0 on end # LPC/eSPI device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller device pci 1f.3 off end # Intel HDA -- cgit v1.2.3