From 39ede0af15f17bf853d7b3208d301dc623251c29 Mon Sep 17 00:00:00 2001 From: Marx Wang Date: Tue, 20 Dec 2022 10:48:33 +0800 Subject: soc/intel/alderlake: Add Raptor Lake device IDs Add system agent ID for RPL QDF#Q2MB/Q2PS TEST=able to build coreboot successfully Signed-off-by: Marx Wang Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121 Reviewed-by: Subrata Banik Reviewed-by: Tarun Tuli Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/include/device/pci_ids.h | 1 + src/soc/intel/alderlake/bootblock/report_platform.c | 1 + src/soc/intel/alderlake/chip.h | 1 + src/soc/intel/alderlake/cpu.c | 1 + src/soc/intel/alderlake/fsp_params.c | 1 + src/soc/intel/alderlake/vr_config.c | 4 ++++ src/soc/intel/common/block/systemagent/systemagent.c | 1 + 7 files changed, 10 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 196f8e6727..548ad00199 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4136,6 +4136,7 @@ #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 #define PCI_DID_INTEL_RPL_P_ID_4 0xa71b +#define PCI_DID_INTEL_RPL_P_ID_5 0xa71c /* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2be75467bd..cc82838799 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -75,6 +75,7 @@ static struct { { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" }, { PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" }, { PCI_DID_INTEL_RPL_P_ID_4, "Raptorlake-P" }, + { PCI_DID_INTEL_RPL_P_ID_5, "Raptorlake-P" }, }; diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a732fe6e8a..82493a7eba 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -136,6 +136,7 @@ static const struct { { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W }, + { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W }, }; /* Types of display ports */ diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 027e978729..4bc0af762f 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -250,6 +250,7 @@ enum adl_cpu_type get_adl_cpu_type(void) PCI_DID_INTEL_RPL_P_ID_2, PCI_DID_INTEL_RPL_P_ID_3, PCI_DID_INTEL_RPL_P_ID_4, + PCI_DID_INTEL_RPL_P_ID_5, }; const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 3463c9f923..03b5686bab 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -515,6 +515,7 @@ static uint16_t get_vccin_aux_imon_iccmax(void) case PCI_DID_INTEL_RPL_P_ID_2: case PCI_DID_INTEL_RPL_P_ID_3: case PCI_DID_INTEL_RPL_P_ID_4: + case PCI_DID_INTEL_RPL_P_ID_5: tdp = get_cpu_tdp(); if (tdp == TDP_45W) return ICC_MAX_TDP_45W; diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index c090641787..bbcae49873 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -130,6 +130,7 @@ static const struct vr_lookup vr_config_ll[] = { { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, @@ -167,6 +168,7 @@ static const struct vr_lookup vr_config_icc[] = { { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) }, @@ -204,6 +206,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, @@ -241,6 +244,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) }, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 90b33358f0..d9634fa999 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -443,6 +443,7 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_RPL_P_ID_2, PCI_DID_INTEL_RPL_P_ID_3, PCI_DID_INTEL_RPL_P_ID_4, + PCI_DID_INTEL_RPL_P_ID_5, 0 }; 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