From 39a84879f5c2c220e91cd7e69587d76cb3438cc0 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Thu, 21 Jan 2021 14:51:50 +0800 Subject: soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE size From the output of 'objdump -x dram.elf', the DRAM blob needs 222K memory, but currently only 208K is reserved for it. Since MT8192 has 1MB SRAM L2C, increase SRAM_L2C_END to 0x00300000, and reorganize regions in SRAM_L2C to have larger DRAM_INIT_CODE (256K). The size of OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE is also increased to 252K. BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Asurada booted successfully BRANCH=none Cq-Depend: chrome-internal:3568265 Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/50017 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8192/include/soc/memlayout.ld | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 2a21dd6ba8..6f964f2331 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -12,7 +12,7 @@ #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) #define DRAM_INIT_CODE(addr, size) \ - REGION(dram_init_code, addr, size, 4) + REGION(dram_init_code, addr, size, 64K) #define DRAM_DMA(addr, size) \ REGION(dram_dma, addr, size, 4K) \ @@ -40,11 +40,16 @@ SECTIONS SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) + /* 4K reserved for BOOTROM until BOOTBLOCK is started */ BOOTBLOCK(0x00201000, 64K) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 188K) - DRAM_INIT_CODE(0x00240000, 208K) - PRERAM_CBFS_CACHE(0x00274000, 48K) - SRAM_L2C_END(0x00280000) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 252K) + /* + * The needed size can be obtained by: + * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz + */ + DRAM_INIT_CODE(0x00250000, 256K) + PRERAM_CBFS_CACHE(0x00290000, 48K) + SRAM_L2C_END(0x00300000) DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) -- cgit v1.2.3