From 374a8b865ccd762381d953644446ec084effd739 Mon Sep 17 00:00:00 2001 From: Jeff Chase Date: Mon, 13 Sep 2021 13:20:37 -0400 Subject: mb/google/hatch/moonbuggy: copy PCIe configuration from genesis The moonbuggy pcie topology is the same as genesis so copy from its device tree and gpios in order to enable these devices. BUG=b:199746414 TEST=lspci Change-Id: I4e916a95047b9f955734f164d7578c520478f5af Signed-off-by: Jeff Chase Reviewed-on: https://review.coreboot.org/c/coreboot/+/57622 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/hatch/variants/moonbuggy/gpio.c | 34 ++++++++-- .../hatch/variants/moonbuggy/overridetree.cb | 77 +++++++++++++++++++--- 2 files changed, 98 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c index 5a911fc4f9..759768b3c8 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c +++ b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c @@ -9,16 +9,34 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_A16, NONE, DEEP), /* A18 : LAN_PE_ISOLATE_ODL */ PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A19 : PCH_PCON0_PDB_ODL */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* A20 : LAN_I350_WAKE# */ + PAD_CFG_GPI_IRQ_WAKE(GPP_A20, NONE, DEEP, LEVEL, INVERT), /* A23 : M2_WLAN_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), /* B5 : LAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : M2_SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : M2_TPU0_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : CLK_PCIE_REQ3 (not connected) */ + PAD_NC(GPP_B8, NONE), + /* B9 : M2_TPU1_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : M2_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* C0 : SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C3 : PCH_MBCLK1_R (i350) */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : PCH_MBDAT1_R (i350) */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* C6: M2_WLAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), /* C7 : LAN_WAKE_ODL */ @@ -30,10 +48,14 @@ static const struct pad_config gpio_table[] = { /* C15 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E2 : Not connected */ + PAD_NC(GPP_E2, NONE), + /* E3 : TPU_RST_PIN40 */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : TPU_RST_PIN42 */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* E9 : PU 10K to PP3300_SOC_A */ + PAD_NC(GPP_E9, NONE), /* E10 : USB_A1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -66,6 +88,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5: PCH_I2C_PCON_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : PCH_I2C_TPU_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C_TPU_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H22 : PWM_PP3300_BIOZZER */ PAD_CFG_GPO(GPP_H22, 0, DEEP), }; diff --git a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb b/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb index a30dad0cdb..2554cfb1a6 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb @@ -182,16 +182,58 @@ chip soc/intel/cannonlake }, }" - # PCIe port 7 for LAN + # PCIe root port 7 for LAN register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" + # PCIe root port 8 for WLAN + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + # Uses CLK SRC 5 + register "PcieClkSrcUsage[5]" = "7" + register "PcieClkSrcClkReq[5]" = "5" + + # PCIe root port 9 for SSD (PCIe Lanes 11, 12) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe root port 10 disabled + register "PcieRpEnable[9]" = "0" + + # PCIe root port 11 TPU1 + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # RP 11 uses CLK SRC 1 + register "PcieClkSrcUsage[4]" = "10" + register "PcieClkSrcClkReq[4]" = "4" + + # PCIe root port 12 TPU0 + register "PcieRpEnable[11]" = "1" + register "PcieRpLtrEnable[11]" = "1" + # RP 11 uses CLK SRC 1 + register "PcieClkSrcUsage[2]" = "11" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe port 13 for i350 NIC (x4) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + # RP 13 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "12" + # RP 13 does not use a source clock request line + # NOTE: Any value other than a valid source-clock-request (0-5) is + # effectively "not connected" + register "PcieClkSrcClkReq[3]" = "0xFF" + # Disable the remaining ports 14-16 + register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" @@ -367,6 +409,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -381,9 +424,9 @@ chip soc/intel/cannonlake device i2c 1a on end end end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net + device pci 1a.0 off end # eMMC + device pci 1c.6 on # PCI Root Port 7 (LAN) + chip drivers/net # RTL8111H Ethernet NIC register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" @@ -393,8 +436,24 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end - end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + end + device pci 1c.7 on # PCI Root Port 8 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot + end + device pci 1d.0 on # PCI Root Port 9 (TPU) + register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot + end + device pci 1d.1 off end # PCI Root Port 10 (Not connected) + device pci 1d.2 on end # PCI Root Port 11 (TPU1) + register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot + device pci 1d.3 on end # PCI Root Port 12 (TPU0) + register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot + device pci 1d.4 on # PCI Root Port 13 (X4 i350 NIC) + register "PcieRpSlotImplemented[12]" = "0" # Built-in + end + device pci 1d.5 on end # PCI Root Port 14 (non-root) + device pci 1d.6 on end # PCI Root Port 15 (non-root) + device pci 1d.7 on end # PCI Root Port 16 (non-root) device pci 1e.3 off end # GSPI #1 end -- cgit v1.2.3