From 36d3586e787addff57bb835c3aa1664b6c8ece94 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 27 Mar 2015 22:55:59 -0700 Subject: arm64: Allow cpu specific early setup Call arm64_cpu_early_setup to allow cpu-specific initialization to be performed. Also, add support for setting SMPEN bit for cortex a57 within arm64_cpu_early_setup. BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully and SMP works for foster Change-Id: Ifa4e6134dbce3ad63046b3dd9b947c3d9134d5e7 Signed-off-by: Patrick Georgi Original-Commit-Id: fe0eac5f416efcf9f7b05388a17444205a8352c0 Original-Change-Id: I28a05a20e6adf084cd0bf94bdd0c3b492632107c Original-Signed-off-by: Furquan Shaikh Original-Reviewed-on: https://chromium-review.googlesource.com/262993 Original-Trybot-Ready: Furquan Shaikh Original-Tested-by: Furquan Shaikh Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9977 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/arch/arm64/Kconfig | 1 + src/arch/arm64/Makefile.inc | 6 +++++- src/arch/arm64/cpu-stubs.c | 25 +++++++++++++++++++++++++ src/arch/arm64/cpu/Kconfig | 23 +++++++++++++++++++++++ src/arch/arm64/cpu/Makefile.inc | 24 ++++++++++++++++++++++++ src/arch/arm64/cpu/cortex_a57.S | 29 +++++++++++++++++++++++++++++ src/arch/arm64/cpu/cortex_a57.h | 26 ++++++++++++++++++++++++++ src/arch/arm64/stage_entry.S | 1 + 8 files changed, 134 insertions(+), 1 deletion(-) create mode 100644 src/arch/arm64/cpu-stubs.c create mode 100644 src/arch/arm64/cpu/Kconfig create mode 100644 src/arch/arm64/cpu/Makefile.inc create mode 100644 src/arch/arm64/cpu/cortex_a57.S create mode 100644 src/arch/arm64/cpu/cortex_a57.h diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 47e7b67456..c51387cb37 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -30,6 +30,7 @@ config ARCH_SPINTABLE depends on ARCH_RAMSTAGE_ARM64 source src/arch/arm64/armv8/Kconfig +source src/arch/arm64/cpu/Kconfig # If a custom bootblock is necessary, this option should be "select"-ed by # the thing that needs it, probably the CPU. diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index c9c93b17ea..7d36bf44f2 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -27,7 +27,7 @@ # Take care of subdirectories ################################################################################ -subdirs-y += armv8/ +subdirs-y += armv8/ cpu/ ################################################################################ # ARM specific options @@ -60,6 +60,7 @@ $(obj)/arch/arm64/id.bootblock.o: $(obj)/build.h bootblock-y += boot.c bootblock-y += c_entry.c bootblock-y += stage_entry.S +bootblock-y += cpu-stubs.c bootblock-y += stages.c bootblock-y += eabi_compat.c bootblock-y += transition.c transition_asm.S @@ -107,6 +108,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) romstage-y += boot.c romstage-y += c_entry.c romstage-y += stage_entry.S +romstage-y += cpu-stubs.c romstage-y += stages.c romstage-y += div0.c romstage-y += eabi_compat.c @@ -149,6 +151,7 @@ ramstage-y += ../../lib/memset.c ramstage-y += ../../lib/memcpy.c ramstage-y += ../../lib/memmove.c ramstage-y += stage_entry.S +ramstage-y += cpu-stubs.c ramstage-$(CONFIG_ARCH_SPINTABLE) += spintable.c spintable_asm.S ramstage-y += transition.c transition_asm.S @@ -158,6 +161,7 @@ rmodules_arm64-y += ../../lib/memmove.c rmodules_arm64-y += eabi_compat.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += stage_entry.S +secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += cpu-stubs.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += startup.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/malloc.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memset.c diff --git a/src/arch/arm64/cpu-stubs.c b/src/arch/arm64/cpu-stubs.c new file mode 100644 index 0000000000..c7b083edfd --- /dev/null +++ b/src/arch/arm64/cpu-stubs.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +void arm64_cpu_early_setup(void); + +void __attribute__((weak)) arm64_cpu_early_setup(void) +{ + /* Default empty implementation */ +} diff --git a/src/arch/arm64/cpu/Kconfig b/src/arch/arm64/cpu/Kconfig new file mode 100644 index 0000000000..fadd48a0d7 --- /dev/null +++ b/src/arch/arm64/cpu/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config ARCH_ARM64_CPU_CORTEX_A57 + bool + default n + depends on ARCH_ARM64 diff --git a/src/arch/arm64/cpu/Makefile.inc b/src/arch/arm64/cpu/Makefile.inc new file mode 100644 index 0000000000..b4f39a5aa4 --- /dev/null +++ b/src/arch/arm64/cpu/Makefile.inc @@ -0,0 +1,24 @@ +################################################################################ +## +## This file is part of the coreboot project. +## +## Copyright 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +################################################################################ + +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) +ramstage-$(CONFIG_ARCH_ARM64_CPU_CORTEX_A57) += cortex_a57.S +endif diff --git a/src/arch/arm64/cpu/cortex_a57.S b/src/arch/arm64/cpu/cortex_a57.S new file mode 100644 index 0000000000..5039d1c59e --- /dev/null +++ b/src/arch/arm64/cpu/cortex_a57.S @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "cortex_a57.h" + +ENTRY(arm64_cpu_early_setup) + mrs x0, CPUECTLR_EL1 + orr x0, x0, #(1 << SMPEN_SHIFT) + msr CPUECTLR_EL1, x0 + isb + ret +ENDPROC(arm64_cpu_early_setup) diff --git a/src/arch/arm64/cpu/cortex_a57.h b/src/arch/arm64/cpu/cortex_a57.h new file mode 100644 index 0000000000..9e66f4d7ca --- /dev/null +++ b/src/arch/arm64/cpu/cortex_a57.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef __ARCH_ARM64_CORTEX_A57_H__ +#define __ARCH_ARM64_CORTEX_A57_H__ + +#define CPUECTLR_EL1 S3_1_c15_c2_1 +#define SMPEN_SHIFT 6 + +#endif /* __ARCH_ARM64_CORTEX_A57_H__ */ diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 6fdd20e992..66e40fbad3 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -209,6 +209,7 @@ ENDPROC(__rmodule_entry) CPU_RESET_ENTRY(arm64_cpu_startup) split_bsp_path + bl arm64_cpu_early_setup setup_sctlr b arm64_c_environment ENDPROC(arm64_cpu_startup) -- cgit v1.2.3