From 36a67e1f3c4e06f24bf340025e39f938bac33f19 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Wed, 20 May 2020 16:44:21 +0530 Subject: mb/google/hatch: Select the fmd files for hatch baseboard This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_HATCH and also renames them to add the baseboard name and layout size tags. BUG=b:154561163 TEST=Built hatch variants and verified that they select the right fmd files. Signed-off-by: V Sowmya Change-Id: I5d99ae28cc972ffa635adf100b756c36e168a8f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41567 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/Kconfig | 6 +-- src/mainboard/google/hatch/chromeos-16MiB.fmd | 43 -------------------- .../google/hatch/chromeos-hatch-16MiB.fmd | 43 ++++++++++++++++++++ .../google/hatch/chromeos-hatch-32MiB.fmd | 47 ++++++++++++++++++++++ src/mainboard/google/hatch/chromeos.fmd | 47 ---------------------- 5 files changed, 93 insertions(+), 93 deletions(-) delete mode 100644 src/mainboard/google/hatch/chromeos-16MiB.fmd create mode 100644 src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd create mode 100644 src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd delete mode 100644 src/mainboard/google/hatch/chromeos.fmd diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 7e3b9e3948..5f6ca70ec9 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -87,11 +87,11 @@ config DRIVER_TPM_SPI_BUS config UART_FOR_CONSOLE default 0 -if ROMSTAGE_SPD_CBFS +if BOARD_GOOGLE_BASEBOARD_HATCH config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 endif if ROMSTAGE_SPD_SMBUS diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd deleted file mode 100644 index 8880a4f9fe..0000000000 --- a/src/mainboard/google/hatch/chromeos-16MiB.fmd +++ /dev/null @@ -1,43 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x400000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x3ff000 - } - SI_BIOS@0x400000 0xc00000 { - RW_SECTION_A@0x0 0x368000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 - } - RW_SECTION_B@0x368000 0x368000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 - } - RW_MISC@0x6D0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 - } - # RW_LEGACY needs to be minimum of 1MB - RW_LEGACY(CBFS)@0x700000 0x100000 - WP_RO@0x800000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 - } - } - } -} diff --git a/src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd b/src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd new file mode 100644 index 0000000000..8880a4f9fe --- /dev/null +++ b/src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd @@ -0,0 +1,43 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0xc00000 { + RW_SECTION_A@0x0 0x368000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x357fc0 + RW_FWID_A@0x367fc0 0x40 + } + RW_SECTION_B@0x368000 0x368000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x357fc0 + RW_FWID_B@0x367fc0 0x40 + } + RW_MISC@0x6D0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS)@0x700000 0x100000 + WP_RO@0x800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd b/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd new file mode 100644 index 0000000000..8368b0a44b --- /dev/null +++ b/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd @@ -0,0 +1,47 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0x1c00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0x1000000 + RW_SECTION_A@0x1000000 0x3e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 + } + RW_SECTION_B@0x13e0000 0x3e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 + } + RW_MISC@0x17c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd deleted file mode 100644 index 8368b0a44b..0000000000 --- a/src/mainboard/google/hatch/chromeos.fmd +++ /dev/null @@ -1,47 +0,0 @@ -FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x400000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x3ff000 - } - SI_BIOS@0x400000 0x1c00000 { - # Place RW_LEGACY at the start of BIOS region such that the rest - # of BIOS regions start at 16MiB boundary. Since this is a 32MiB - # SPI flash only the top 16MiB actually gets memory mapped. - RW_LEGACY(CBFS)@0x0 0x1000000 - RW_SECTION_A@0x1000000 0x3e0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 - } - RW_SECTION_B@0x13e0000 0x3e0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 - } - RW_MISC@0x17c0000 0x40000 { - UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 - } - RW_ELOG(PRESERVE)@0x30000 0x4000 - RW_SHARED@0x34000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 - } - # Make WP_RO region align with SPI vendor - # memory protected range specification. - WP_RO@0x1800000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 - } - } - } -} -- cgit v1.2.3