From 369b9ad78705fcc2bfa0ad6672e61c2d3cc135f8 Mon Sep 17 00:00:00 2001 From: Teddy Shih Date: Mon, 14 Mar 2022 14:40:08 +0800 Subject: mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption To achieve low power consumption, we disable unused PCIe and SATA pins at beadrix/overridetree.cb according to baseboard/devicetree.cb and mainboard schematic. Original measured beadrix board's power consumption is about 250 mW. After we disable unused PCIe and SATA pins, as well as, enable the other low power MUX CL (3487086: USB MUX: Update low power mode of MUX anx7447 used as MUX only | https://chromium-review.googlesource.com/c/chromiumos/platform/ec/ +/3487086), the measured power consumption achieves about 110 ~ 116 mW, as well as, meets Google battery life for 14 days in the suspend state and Intel low power consumption about 116 mW. BRANCH=dedede BUG=b:204882915 TEST=on beadrix, measured power consumption meets Intel power consumption. Signed-off-by: Teddy Shih Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776 Reviewed-by: Teddy Shih Reviewed-by: Paul Menzel Reviewed-by: Super Ni Reviewed-by: Karthik Ramasubramanian Reviewed-by: Ivan Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/beadrix/overridetree.cb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index d5b37d4550..8a12e4140d 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -1,7 +1,9 @@ chip soc/intel/jasperlake # USB Port Configuration + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable unused USB2P_5 and USB2N_5 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable unused USB2P_7 and USB2N_7 # Intel Common SoC Config #+-------------------+---------------------------+ @@ -115,6 +117,7 @@ chip soc/intel/jasperlake device i2c 15 on end end end # I2C 0 + device pci 17.0 off end # SATA. Baseboard/devicetree.cb is off device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -128,6 +131,8 @@ chip soc/intel/jasperlake device i2c 1a on end end end # I2C 4 + device pci 1c.6 off end # PCI Express Root Port 7 / SATA_0. Baseboard/devicetree.cb is off + device pci 1c.7 off end # PCI Express Root Port 8 / SATA_1 device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98360A"" -- cgit v1.2.3