From 35325e1688a74756c90bd5e30ef6f07f0172e85f Mon Sep 17 00:00:00 2001 From: "sh.kim" Date: Fri, 1 Dec 2017 16:09:50 +0900 Subject: mb/google/poppy/variants/nautilus: Change USB2 phy setting In order to pass USB2 eye diagram, some USB2 port PHY registers needs to be changed. Port1 (Type-A): USB2_PORT_SHORT Port2 (BT): USB2_PORT_SHORT Port6 (H1): USB2_PORT_SHORT Port7 (Camera): USB2_PORT_SHORT BUG=none BRANCH=master TEST=emerge-nautilus coreboot and do eye-diagram test Signed-off-by: sh.kim Change-Id: I174e5bf96a53bb210481fb88298d5341f6c11dec Reviewed-on: https://review.coreboot.org/22686 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 46b0946c2b..50137896aa 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -163,11 +163,11 @@ chip soc/intel/skylake register "PcieRpLtrEnable[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 + register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 -- cgit v1.2.3