From 33c10f8c32a16701ad601d491322fb2468111b9b Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Thu, 30 Oct 2014 14:49:53 +0000 Subject: urara: Configure UART line control to 8N1 8bit, 1 stop bit, no parity BUG=chrome-os-partner:31438 TEST=built urara bootblock and ran it on the Pistachio FPGA, observed expected console output. BRANCH=none Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785 Signed-off-by: Stefan Reinauer Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4 Original-Signed-off-by: Ionela Voinescu Original-Reviewed-on: https://chromium-review.googlesource.com/226551 Original-Reviewed-by: Vadim Bendebury Original-Commit-Queue: Vadim Bendebury Original-Tested-by: Vadim Bendebury Reviewed-on: http://review.coreboot.org/9185 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/mainboard/google/urara/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index 231c97e3c2..bde26d6524 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -46,4 +46,8 @@ config DRAM_SIZE_MB int default 256 +config TTYS0_LCS + int + default 3 + endif -- cgit v1.2.3