From 31f383686a5aea58092330b29a9a7f128c2e3889 Mon Sep 17 00:00:00 2001 From: Sugnan Prabhu S Date: Tue, 16 Mar 2021 18:05:13 +0530 Subject: mb/google/brya: Enable S0ix This change enables S0ix for brya platform. BUG=b:181843816 TEST=Built image and booted to kernel. Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb Signed-off-by: Sugnan Prabhu S Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526 Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/baseboard/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 33be8623f7..3155d04f82 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -14,6 +14,9 @@ chip soc/intel/alderlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # S0ix enable + register "s0ix_enable" = "1" + # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 -- cgit v1.2.3