From 31998020458af821cb61d0000ee2cbd0293958f6 Mon Sep 17 00:00:00 2001 From: Jincheng Li Date: Wed, 13 Mar 2024 15:06:26 +0800 Subject: soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms DDR support codes across generations are similar. Share the codes to improve code reuse. TEST=intel/archercity CRB Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf Signed-off-by: Jincheng Li Reviewed-on: https://review.coreboot.org/c/coreboot/+/81219 Reviewed-by: Shuo Liu Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/xeon_sp/Makefile.mk | 2 +- src/soc/intel/xeon_sp/cpx/Makefile.mk | 2 +- src/soc/intel/xeon_sp/cpx/ddr.c | 89 ----------------------- src/soc/intel/xeon_sp/cpx/include/soc/ddr.h | 53 -------------- src/soc/intel/xeon_sp/ddr.c | 107 ++++++++++++++++++++++++++++ src/soc/intel/xeon_sp/include/soc/ddr.h | 60 ++++++++++++++++ src/soc/intel/xeon_sp/spr/Makefile.mk | 2 +- src/soc/intel/xeon_sp/spr/ddr.c | 93 ------------------------ src/soc/intel/xeon_sp/spr/include/soc/ddr.h | 57 --------------- src/soc/intel/xeon_sp/spr/romstage.c | 5 -- 10 files changed, 170 insertions(+), 300 deletions(-) delete mode 100644 src/soc/intel/xeon_sp/cpx/ddr.c delete mode 100644 src/soc/intel/xeon_sp/cpx/include/soc/ddr.h create mode 100644 src/soc/intel/xeon_sp/ddr.c create mode 100644 src/soc/intel/xeon_sp/include/soc/ddr.h delete mode 100644 src/soc/intel/xeon_sp/spr/ddr.c delete mode 100644 src/soc/intel/xeon_sp/spr/include/soc/ddr.h diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index 58915447b7..1f96bb7f3b 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -7,7 +7,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg bootblock-y += bootblock.c spi.c lpc.c pch.c report_platform.c -romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c +romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c lockdown.c finalize.c diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index 911cf66e4a..095ad59af4 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -5,7 +5,7 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c ddr.c soc_util.c +romstage-y += romstage.c soc_util.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/cpx/ddr.c b/src/soc/intel/xeon_sp/cpx/ddr.c deleted file mode 100644 index 990711f090..0000000000 --- a/src/soc/intel/xeon_sp/cpx/ddr.c +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include - -uint32_t get_ddr_voltage(uint8_t DdrVoltage) -{ - /* SPD Byte 11: Module Nominal Voltage, currently DDR4 only supports 1.2V. - Either Bit 0 or Bit 1 is set, return 1.2V */ - if (DdrVoltage & 0x3) - return 1200; - return 0; -} - -uint16_t get_max_memory_speed(uint32_t commonTck) -{ - if (commonTck <= DDR_8400_TCK_MIN) - return 8400; - else if (commonTck <= DDR_6400_TCK_MIN) - return 6400; - else if (commonTck <= DDR_6000_TCK_MIN) - return 6000; - else if (commonTck <= DDR_5600_TCK_MIN) - return 5600; - else if (commonTck <= DDR_5200_TCK_MIN) - return 5200; - else if (commonTck <= DDR_4800_TCK_MIN) - return 4800; - else if (commonTck <= DDR_4400_TCK_MIN) - return 4400; - else if (commonTck <= DDR_4266_TCK_MIN) - return 4266; - else if (commonTck <= DDR_4200_TCK_MIN) - return 4200; - else if (commonTck <= DDR_4000_TCK_MIN) - return 4000; - else if (commonTck <= DDR_3800_TCK_MIN) - return 3800; - else if (commonTck <= DDR_3733_TCK_MIN) - return 3733; - else if (commonTck <= DDR_3600_TCK_MIN) - return 3600; - else if (commonTck <= DDR_3466_TCK_MIN) - return 3466; - else if (commonTck <= DDR_3400_TCK_MIN) - return 3400; - else if (commonTck <= DDR_3200_TCK_MIN) - return 3200; - else if (commonTck <= DDR_3000_TCK_MIN) - return 3000; - else if (commonTck <= DDR_2933_TCK_MIN) - return 2933; - else if (commonTck <= DDR_2800_TCK_MIN) - return 2800; - else if (commonTck <= DDR_2666_TCK_MIN) - return 2666; - else if (commonTck <= DDR_2600_TCK_MIN) - return 2600; - else if (commonTck <= DDR_2400_TCK_MIN) - return 2400; - else if (commonTck <= DDR_2200_TCK_MIN) - return 2200; - else if (commonTck <= DDR_2133_TCK_MIN) - return 2133; - else if (commonTck <= DDR_2000_TCK_MIN) - return 2000; - else if (commonTck <= DDR_1866_TCK_MIN) - return 1866; - else if (commonTck <= DDR_1800_TCK_MIN) - return 1800; - else if (commonTck <= DDR_1600_TCK_MIN) - return 1600; - else if (commonTck <= DDR_1400_TCK_MIN) - return 1400; - else if (commonTck <= DDR_1333_TCK_MIN) - return 1333; - else if (commonTck <= DDR_1200_TCK_MIN) - return 1200; - else if (commonTck <= DDR_1066_TCK_MIN) - return 1066; - else if (commonTck <= DDR_1000_TCK_MIN) - return 1000; - else - return 800; -} - -__weak bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot) -{ - return false; -} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h deleted file mode 100644 index 0ef6ded124..0000000000 --- a/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _CPX_DDR_H_ -#define _CPX_DDR_H_ - -#include - -/* DDR_*_TCK_MIN are in picoseconds */ -#define DDR_800_TCK_MIN 2500 -#define DDR_1000_TCK_MIN 2000 -#define DDR_1066_TCK_MIN 1875 -#define DDR_1200_TCK_MIN 1667 -#define DDR_1333_TCK_MIN 1500 -#define DDR_1400_TCK_MIN 1429 -#define DDR_1600_TCK_MIN 1250 -#define DDR_1800_TCK_MIN 1110 -#define DDR_1866_TCK_MIN 1071 -#define DDR_2000_TCK_MIN 1000 -#define DDR_2133_TCK_MIN 938 -#define DDR_2200_TCK_MIN 909 -#define DDR_2400_TCK_MIN 833 -#define DDR_2600_TCK_MIN 769 -#define DDR_2666_TCK_MIN 750 -#define DDR_2800_TCK_MIN 714 -#define DDR_2933_TCK_MIN 682 -#define DDR_3000_TCK_MIN 667 -#define DDR_3200_TCK_MIN 625 -#define DDR_3400_TCK_MIN 589 -#define DDR_3466_TCK_MIN 577 -#define DDR_3600_TCK_MIN 556 -#define DDR_3733_TCK_MIN 536 -#define DDR_3800_TCK_MIN 527 -#define DDR_4000_TCK_MIN 500 -#define DDR_4200_TCK_MIN 477 -#define DDR_4266_TCK_MIN 469 -#define DDR_4400_TCK_MIN 455 -#define DDR_4800_TCK_MIN 417 -#define DDR_5200_TCK_MIN 385 -#define DDR_5600_TCK_MIN 358 -#define DDR_6000_TCK_MIN 334 -#define DDR_6400_TCK_MIN 313 -#define DDR_6800_TCK_MIN 295 -#define DDR_7200_TCK_MIN 278 -#define DDR_7600_TCK_MIN 264 -#define DDR_8000_TCK_MIN 250 -#define DDR_8400_TCK_MIN 239 - -uint16_t get_max_memory_speed(uint32_t commonTck); -uint32_t get_ddr_voltage(uint8_t DdrVoltage); - -bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot); - -#endif /* _CPX_DDR_H_ */ diff --git a/src/soc/intel/xeon_sp/ddr.c b/src/soc/intel/xeon_sp/ddr.c new file mode 100644 index 0000000000..de248ca13b --- /dev/null +++ b/src/soc/intel/xeon_sp/ddr.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +uint32_t get_ddr_voltage(uint8_t ddr_voltage) +{ + /* SPD Byte 11: Module Nominal Voltage, currently DDR4 only supports 1.2V. + Either Bit 0 or Bit 1 is set, return 1.2V */ + if (ddr_voltage & 0x3) + return 1200; + return 0; +} + +unsigned int get_ddr_millivolt(unsigned int ddr_voltage) +{ + switch (ddr_voltage) { + case SPD_VDD_DDR4: + return 1200; + case SPD_VDD_DDR5: + return 1100; + default: + return 0; + } +} + +unsigned int get_max_memory_speed(unsigned int common_tck) +{ + if (common_tck <= DDR_8400_TCK_MIN) + return 8400; + else if (common_tck <= DDR_7600_TCK_MIN) + return 7600; + else if (common_tck <= DDR_7200_TCK_MIN) + return 7200; + else if (common_tck <= DDR_6800_TCK_MIN) + return 6800; + else if (common_tck <= DDR_6400_TCK_MIN) + return 6400; + else if (common_tck <= DDR_6000_TCK_MIN) + return 6000; + else if (common_tck <= DDR_5600_TCK_MIN) + return 5600; + else if (common_tck <= DDR_5200_TCK_MIN) + return 5200; + else if (common_tck <= DDR_4800_TCK_MIN) + return 4800; + else if (common_tck <= DDR_4400_TCK_MIN) + return 4400; + else if (common_tck <= DDR_4266_TCK_MIN) + return 4266; + else if (common_tck <= DDR_4200_TCK_MIN) + return 4200; + else if (common_tck <= DDR_4000_TCK_MIN) + return 4000; + else if (common_tck <= DDR_3800_TCK_MIN) + return 3800; + else if (common_tck <= DDR_3733_TCK_MIN) + return 3733; + else if (common_tck <= DDR_3600_TCK_MIN) + return 3600; + else if (common_tck <= DDR_3466_TCK_MIN) + return 3466; + else if (common_tck <= DDR_3400_TCK_MIN) + return 3400; + else if (common_tck <= DDR_3200_TCK_MIN) + return 3200; + else if (common_tck <= DDR_3000_TCK_MIN) + return 3000; + else if (common_tck <= DDR_2933_TCK_MIN) + return 2933; + else if (common_tck <= DDR_2800_TCK_MIN) + return 2800; + else if (common_tck <= DDR_2666_TCK_MIN) + return 2666; + else if (common_tck <= DDR_2600_TCK_MIN) + return 2600; + else if (common_tck <= DDR_2400_TCK_MIN) + return 2400; + else if (common_tck <= DDR_2200_TCK_MIN) + return 2200; + else if (common_tck <= DDR_2133_TCK_MIN) + return 2133; + else if (common_tck <= DDR_2000_TCK_MIN) + return 2000; + else if (common_tck <= DDR_1866_TCK_MIN) + return 1866; + else if (common_tck <= DDR_1800_TCK_MIN) + return 1800; + else if (common_tck <= DDR_1600_TCK_MIN) + return 1600; + else if (common_tck <= DDR_1400_TCK_MIN) + return 1400; + else if (common_tck <= DDR_1333_TCK_MIN) + return 1333; + else if (common_tck <= DDR_1200_TCK_MIN) + return 1200; + else if (common_tck <= DDR_1066_TCK_MIN) + return 1066; + else if (common_tck <= DDR_1000_TCK_MIN) + return 1000; + else + return 800; +} + +__weak bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot) +{ + return false; +} diff --git a/src/soc/intel/xeon_sp/include/soc/ddr.h b/src/soc/intel/xeon_sp/include/soc/ddr.h new file mode 100644 index 0000000000..bb10caaf1f --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/ddr.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_DDR_H_ +#define _SOC_DDR_H_ + +#include + +/* SPD Byte 11: Module Nominal Voltage + * currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */ +#define SPD_VDD_DDR4 3 +#define SPD_VDD_DDR5 0 +#define SPD_TYPE_DDR5 0x12 + +/* DDR_*_TCK_MIN are in picoseconds */ +#define DDR_800_TCK_MIN 2500 +#define DDR_1000_TCK_MIN 2000 +#define DDR_1066_TCK_MIN 1875 +#define DDR_1200_TCK_MIN 1667 +#define DDR_1333_TCK_MIN 1500 +#define DDR_1400_TCK_MIN 1429 +#define DDR_1600_TCK_MIN 1250 +#define DDR_1800_TCK_MIN 1110 +#define DDR_1866_TCK_MIN 1071 +#define DDR_2000_TCK_MIN 1000 +#define DDR_2133_TCK_MIN 938 +#define DDR_2200_TCK_MIN 909 +#define DDR_2400_TCK_MIN 833 +#define DDR_2600_TCK_MIN 769 +#define DDR_2666_TCK_MIN 750 +#define DDR_2800_TCK_MIN 714 +#define DDR_2933_TCK_MIN 682 +#define DDR_3000_TCK_MIN 667 +#define DDR_3200_TCK_MIN 625 +#define DDR_3400_TCK_MIN 589 +#define DDR_3466_TCK_MIN 577 +#define DDR_3600_TCK_MIN 556 +#define DDR_3733_TCK_MIN 536 +#define DDR_3800_TCK_MIN 527 +#define DDR_4000_TCK_MIN 500 +#define DDR_4200_TCK_MIN 477 +#define DDR_4266_TCK_MIN 469 +#define DDR_4400_TCK_MIN 455 +#define DDR_4800_TCK_MIN 417 +#define DDR_5200_TCK_MIN 385 +#define DDR_5600_TCK_MIN 358 +#define DDR_6000_TCK_MIN 334 +#define DDR_6400_TCK_MIN 313 +#define DDR_6800_TCK_MIN 295 +#define DDR_7200_TCK_MIN 278 +#define DDR_7600_TCK_MIN 264 +#define DDR_8000_TCK_MIN 250 +#define DDR_8400_TCK_MIN 239 + +unsigned int get_max_memory_speed(unsigned int commonTck); +unsigned int get_ddr_millivolt(unsigned int ddr_voltage); +uint32_t get_ddr_voltage(uint8_t DdrVoltage); + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot); + +#endif /* _SOC_DDR_H_ */ diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index fc8ab1713d..d999f30661 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c soc_util.c ddr.c +romstage-y += romstage.c soc_util.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/spr/ddr.c b/src/soc/intel/xeon_sp/spr/ddr.c deleted file mode 100644 index ff61a7e8a4..0000000000 --- a/src/soc/intel/xeon_sp/spr/ddr.c +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include - -unsigned int get_ddr_millivolt(unsigned int ddr_voltage) -{ - switch (ddr_voltage) { - case SPD_VDD_DDR4: - return 1200; - case SPD_VDD_DDR5: - return 1100; - default: - return 0; - } -} - -unsigned int get_max_memory_speed(unsigned int commonTck) -{ - if (commonTck <= DDR_8400_TCK_MIN) - return 8400; - else if (commonTck <= DDR_7600_TCK_MIN) - return 7600; - else if (commonTck <= DDR_7200_TCK_MIN) - return 7200; - else if (commonTck <= DDR_6800_TCK_MIN) - return 6800; - else if (commonTck <= DDR_6400_TCK_MIN) - return 6400; - else if (commonTck <= DDR_6000_TCK_MIN) - return 6000; - else if (commonTck <= DDR_5600_TCK_MIN) - return 5600; - else if (commonTck <= DDR_5200_TCK_MIN) - return 5200; - else if (commonTck <= DDR_4800_TCK_MIN) - return 4800; - else if (commonTck <= DDR_4400_TCK_MIN) - return 4400; - else if (commonTck <= DDR_4266_TCK_MIN) - return 4266; - else if (commonTck <= DDR_4200_TCK_MIN) - return 4200; - else if (commonTck <= DDR_4000_TCK_MIN) - return 4000; - else if (commonTck <= DDR_3800_TCK_MIN) - return 3800; - else if (commonTck <= DDR_3733_TCK_MIN) - return 3733; - else if (commonTck <= DDR_3600_TCK_MIN) - return 3600; - else if (commonTck <= DDR_3466_TCK_MIN) - return 3466; - else if (commonTck <= DDR_3400_TCK_MIN) - return 3400; - else if (commonTck <= DDR_3200_TCK_MIN) - return 3200; - else if (commonTck <= DDR_3000_TCK_MIN) - return 3000; - else if (commonTck <= DDR_2933_TCK_MIN) - return 2933; - else if (commonTck <= DDR_2800_TCK_MIN) - return 2800; - else if (commonTck <= DDR_2666_TCK_MIN) - return 2666; - else if (commonTck <= DDR_2600_TCK_MIN) - return 2600; - else if (commonTck <= DDR_2400_TCK_MIN) - return 2400; - else if (commonTck <= DDR_2200_TCK_MIN) - return 2200; - else if (commonTck <= DDR_2133_TCK_MIN) - return 2133; - else if (commonTck <= DDR_2000_TCK_MIN) - return 2000; - else if (commonTck <= DDR_1866_TCK_MIN) - return 1866; - else if (commonTck <= DDR_1800_TCK_MIN) - return 1800; - else if (commonTck <= DDR_1600_TCK_MIN) - return 1600; - else if (commonTck <= DDR_1400_TCK_MIN) - return 1400; - else if (commonTck <= DDR_1333_TCK_MIN) - return 1333; - else if (commonTck <= DDR_1200_TCK_MIN) - return 1200; - else if (commonTck <= DDR_1066_TCK_MIN) - return 1066; - else if (commonTck <= DDR_1000_TCK_MIN) - return 1000; - else - return 800; -} diff --git a/src/soc/intel/xeon_sp/spr/include/soc/ddr.h b/src/soc/intel/xeon_sp/spr/include/soc/ddr.h deleted file mode 100644 index f2dc5c8998..0000000000 --- a/src/soc/intel/xeon_sp/spr/include/soc/ddr.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SPR_DDR_H_ -#define _SPR_DDR_H_ - -#include - -/* SPD Byte 11: Module Nominal Voltage - * currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */ -#define SPD_VDD_DDR4 3 -#define SPD_VDD_DDR5 0 -#define SPD_TYPE_DDR5 0x12 - -/* DDR_*_TCK_MIN are in picoseconds */ -#define DDR_1000_TCK_MIN 2000 -#define DDR_1066_TCK_MIN 1875 -#define DDR_1200_TCK_MIN 1667 -#define DDR_1333_TCK_MIN 1500 -#define DDR_1400_TCK_MIN 1429 -#define DDR_1600_TCK_MIN 1250 -#define DDR_1800_TCK_MIN 1110 -#define DDR_1866_TCK_MIN 1071 -#define DDR_2000_TCK_MIN 1000 -#define DDR_2133_TCK_MIN 938 -#define DDR_2200_TCK_MIN 909 -#define DDR_2400_TCK_MIN 833 -#define DDR_2600_TCK_MIN 769 -#define DDR_2666_TCK_MIN 750 -#define DDR_2800_TCK_MIN 714 -#define DDR_2933_TCK_MIN 682 -#define DDR_3000_TCK_MIN 667 -#define DDR_3200_TCK_MIN 625 -#define DDR_3400_TCK_MIN 589 -#define DDR_3466_TCK_MIN 577 -#define DDR_3600_TCK_MIN 556 -#define DDR_3733_TCK_MIN 536 -#define DDR_3800_TCK_MIN 527 -#define DDR_4000_TCK_MIN 500 -#define DDR_4200_TCK_MIN 477 -#define DDR_4266_TCK_MIN 469 -#define DDR_4400_TCK_MIN 455 -#define DDR_4800_TCK_MIN 417 -#define DDR_5200_TCK_MIN 385 -#define DDR_5600_TCK_MIN 358 -#define DDR_6000_TCK_MIN 334 -#define DDR_6400_TCK_MIN 313 -#define DDR_6800_TCK_MIN 295 -#define DDR_7200_TCK_MIN 278 -#define DDR_7600_TCK_MIN 264 -#define DDR_8000_TCK_MIN 250 -#define DDR_8400_TCK_MIN 239 - -unsigned int get_max_memory_speed(unsigned int commonTck); -unsigned int get_ddr_millivolt(unsigned int ddr_voltage); -bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot); - -#endif /* _SPR_DDR_H_ */ diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 74976b362e..3b38828492 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -32,11 +32,6 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd) /* Default weak implementation */ } -bool __weak mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) -{ - return false; -} - /* * Search from VPD_RW first then VPD_RO for UPD config variables, * overwrites them from VPD if it's found. -- cgit v1.2.3