From 30fc6676dbfee43009b4110eb1ff7b4e03c91a37 Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Mon, 26 Jan 2015 13:29:34 +0000 Subject: pistachio: increase size of bootblock to 18 KB With the added code for clock and MFIOs setup, bootblock now exceeds 16KB. This patch increases the allowed limit to 18KB. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works as expected BRANCH=none Change-Id: I166f882bd3db446bcd6f9e1f828cab22266c6ac7 Signed-off-by: Stefan Reinauer Original-Commit-Id: da95db5ed348419b7905dc1ab68fd64d7b2eb5e0 Original-Change-Id: I0cacc6163f21ae3673c2716b12dde66bd48290f9 Original-Signed-off-by: Ionela Voinescu Original-Reviewed-on: https://chromium-review.googlesource.com/243213 Original-Reviewed-by: David Hendricks Reviewed-on: http://review.coreboot.org/9665 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 75387624cb..5b50a0a365 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -28,9 +28,9 @@ SECTIONS /* GRAM becomes the SRAM. */ SRAM_START(0x9a000000) - BOOTBLOCK(0x9a000000, 16K) - ROMSTAGE(0x9a004000, 36K) - CBFS_CACHE(0x9a00d000, 76K) + BOOTBLOCK(0x9a000000, 18K) + ROMSTAGE(0x9a004800, 36K) + CBFS_CACHE(0x9a00d800, 74K) SRAM_END(0x9a020000) /* Let's use SRAM for stack and CBMEM console. */ -- cgit v1.2.3