From 2f084d4904c26ef0cd87ecd46b83a8fef3871290 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 19 Oct 2005 18:19:26 +0000 Subject: initial support for apache. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/momentum/apache/Config.lb | 107 +++++++++++++++++++++++ src/mainboard/momentum/apache/Options.lb | 141 +++++++++++++++++++++++++++++++ src/mainboard/momentum/apache/chip.h | 5 ++ 3 files changed, 253 insertions(+) create mode 100644 src/mainboard/momentum/apache/Config.lb create mode 100644 src/mainboard/momentum/apache/Options.lb create mode 100644 src/mainboard/momentum/apache/chip.h diff --git a/src/mainboard/momentum/apache/Config.lb b/src/mainboard/momentum/apache/Config.lb new file mode 100644 index 0000000000..45d41dda38 --- /dev/null +++ b/src/mainboard/momentum/apache/Config.lb @@ -0,0 +1,107 @@ +## +## Config file for the momentum apache +## + +## +## Early board initialization, called from ppc_main() +## +#initobject init.c + +arch ppc end + +chip northbridge/ibm/cpc925 + device pci_domain 0 on + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # pxhd1 + device pci 00.0 on end + device pci 00.1 on end + device pci 00.2 on + chip drivers/generic/generic + device pci 04.0 on end + device pci 04.1 on end + end + end + device pci 00.3 on end + end + end + device pci 06.0 on end + chip southbridge/intel/ich5r # ich5r + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 off end + device pci 1d.7 on end + device pci 1e.0 on + chip drivers/ati/ragexl + device pci 0c.0 on end + end + end + device pci 1f.0 on + chip superio/NSC/pc87427 + device pnp 2e.0 off end + device pnp 2e.2 on +# io 0x60 = 0x2f8 +# irq 0x70 = 3 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on +# io 0x60 = 0x3f8 +# irq 0x70 = 4 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 on + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a off end + device pnp 2e.f on end + device pnp 2e.10 off end + device pnp 2e.14 off end + end + end + device pci 1f.1 on end + device pci 1f.2 off end + device pci 1f.3 on end + device pci 1f.5 off end + device pci 1f.6 off end + register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO" + register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW" + register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT" + end + end + device apic_cluster 0 on + chip cpu/ppc/ppc970 # cpu 0 + end + chip cpu/ppc/ppc970 # cpu 1 + end + end +end + + +chip cpu/ppc/ppc4xx + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/winbond/w83c553 + device pci 9.0 on end # ISA bridge + device pci 9.1 on end # IDE contoller + end + device pci e.0 on end + end +end + +## +## Build the objects we have code for in this directory. +## + +addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a" +makedefine CFLAGS += -msoft-float diff --git a/src/mainboard/momentum/apache/Options.lb b/src/mainboard/momentum/apache/Options.lb new file mode 100644 index 0000000000..3275aa297d --- /dev/null +++ b/src/mainboard/momentum/apache/Options.lb @@ -0,0 +1,141 @@ +## +## Config file for the Embedded Planet EP405PC Computing Engine +## + +uses PCIC0_CFGADDR +uses PCIC0_CFGDATA +uses ISA_IO_BASE +uses ISA_MEM_BASE +uses TTYS0_BASE +uses _IO_BASE + +uses CPU_OPT +uses CROSS_COMPILE +uses HAVE_OPTION_TABLE +uses CONFIG_COMPRESS +uses CONFIG_CHIP_CONFIGURE +uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_USE_INIT +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD TTYS0_DIV +uses NO_POST +uses CONFIG_IDE +uses CONFIG_FS_STREAM +uses CONFIG_FS_EXT2 +uses CONFIG_FS_ISO9660 +uses CONFIG_FS_FAT +uses AUTOBOOT_CMDLINE +uses CONFIG_SYS_CLK_FREQ +uses IDE_BOOT_DRIVE +#uses IDE_SWAB +uses IDE_OFFSET +uses ROM_SIZE +uses _RESET +uses _EXCEPTION_VECTORS +uses _ROMBASE +uses _ROMSTART +uses _RAMBASE +#uses _RAMSTART +uses EMBEDDED_RAM_SIZE +uses STACK_SIZE HEAP_SIZE + +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY + +## +## Set PCI configuration register addresses +## +default PCIC0_CFGADDR=0xeec00000 +default PCIC0_CFGDATA=0xeec00004 + +## +## Set PCI/ISA I/O and memory base address +## +default ISA_IO_BASE=0xe8000000 +default ISA_MEM_BASE=0x80000000 +default _IO_BASE=ISA_IO_BASE + +## +## HACK ALERT: the UART0 registers are not in the PCI I/O address space +## but both IDE and UART use the same routines for I/O (inb/outb). To get +## around this we set TTYSO_BASE to the difference between the two. +## +default TTYS0_BASE=0xef600300-ISA_IO_BASE + +## Enable PPC405 instructions +default CPU_OPT="-mcpu=405" +#default CPU_OPT="" + +## Use stage 1 initialization code +default CONFIG_USE_INIT=1 + +## Use chip configuration +default CONFIG_CHIP_CONFIGURE=1 + +## We don't use compressed image +default CONFIG_COMPRESS=0 + +## Turn off POST codes +default NO_POST=1 + +## Enable serial console +default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_CONSOLE_SERIAL8250=1 +# Divisor of 69 == 9600 baud due to weird clocking +default TTYS0_DIV=69 +default TTYS0_BAUD=9600 + +## Boot linux from IDE +default CONFIG_IDE=1 +default CONFIG_FS_STREAM=1 +default CONFIG_FS_EXT2=1 +default CONFIG_FS_ISO9660=1 +default CONFIG_FS_FAT=1 +default AUTOBOOT_CMDLINE="hda1:/vmlinuz" + +default ROM_SIZE=1048576 + +## Board has fixed size RAM +default EMBEDDED_RAM_SIZE=64*1024*1024 + +## LinuxBIOS C code runs at this location in RAM +default _RAMBASE=0x00100000 + +## +## Use a 64K stack +## +default STACK_SIZE=0x10000 + +## +## Use a 64K heap +## +default HEAP_SIZE=0x10000 + +## +## System clock +## +default CONFIG_SYS_CLK_FREQ=33 + +## +default _ROMBASE=0xfff00000 + +## Reset vector address +default _RESET=0xfffffffc + +## Exception vectors +default _EXCEPTION_VECTORS=_ROMBASE+0x100 + +## linuxBIOS ROM start address +default _ROMSTART=0xfff03000 + +## linuxBIOS C code runs at this location in RAM +default _RAMBASE=0x00100000 + +### End Options.lb +end diff --git a/src/mainboard/momentum/apache/chip.h b/src/mainboard/momentum/apache/chip.h new file mode 100644 index 0000000000..a76eb645f9 --- /dev/null +++ b/src/mainboard/momentum/apache/chip.h @@ -0,0 +1,5 @@ +struct chip_operations mainboard_momentum_apache_ops; + +struct mainboard_momentum_apache_config { + int nothing; +}; -- cgit v1.2.3