From 2ebfb79d336c864eb93619fb2980e5b9fc90b014 Mon Sep 17 00:00:00 2001 From: Shon Wang Date: Tue, 25 Jun 2024 16:01:00 +0800 Subject: mb/google/brask/var/bujia: Configure Serial IO UARTs Mode This patch configures Serial IO UARTs mode as below. UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design. BUG=b:338917836 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38 Signed-off-by: Shon Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205 Reviewed-by: Eric Lai Reviewed-by: Derek Huang Reviewed-by: Varshit Pandya Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/bujia/overridetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index 252d82f8a5..4255296ff6 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -46,6 +46,12 @@ chip soc/intel/alderlake [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, -- cgit v1.2.3