From 2d12a901fbbb4cc5ee5255616cd9960223c310e0 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 17 Dec 2017 21:01:54 -0800 Subject: mb/google/poppy: Configure pen reset and eject lines This change configures the GPIOs for pen reset and eject lines and exports required properties using ACPI table. BUG=b:70773138 Change-Id: I52f6c3dced54259cde8ee6753275622622e15954 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/22926 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 5 +++++ src/mainboard/google/poppy/variants/baseboard/gpio.c | 12 ++++++------ 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 22ef9aac55..ceb0c95a0e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -308,6 +308,11 @@ chip soc/intel/skylake register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" + register "generic.wake" = "GPE0_DW1_12" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" + register "generic.reset_delay_ms" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index a0dbbee1f6..d0e2097b0d 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -166,8 +166,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), /* D2 : SPI1_MISO ==> PEN_PDCT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP), - /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + /* D3 : SPI1_MOSI ==> PEN_RST_L */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), /* D4 : FASHTRIG ==> NC */ PAD_CFG_NC(GPP_D4), /* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */ @@ -176,16 +176,16 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> NC */ PAD_CFG_NC(GPP_D7), - /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + /* D8 : ISH_I2C1_SCL ==> PEN_EJECT_ODL -- for notification */ + PAD_CFG_GPI(GPP_D8, NONE, PLTRST), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), - /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + /* D12 : ISH_SPI_MOSI ==> PEN_EJECT_ODL -- for wake event */ + PAD_CFG_GPI_ACPI_SCI(GPP_D12, NONE, DEEP, INVERT), /* D13 : ISH_UART0_RXD ==> NC */ PAD_CFG_NC(GPP_D13), /* D14 : ISH_UART0_TXD ==> NC */ -- cgit v1.2.3